Motorola CPCI-6115 User Manual
Cpci-6115 compactpci single board computer
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Table of contents
Document Outline
- CPCI-6115 CompactPCI Single Board Computer
- Contents
- List of Tables
- List of Figures
- About this Manual
- Safety Notes
- Sicherheitshinweise
- Introduction
- Hardware Preparation and Installation
- 2.1 Overview
- 2.2 Unpacking and Inspecting the Board
- 2.3 Environmental, Power, and Thermal Requirements
- 2.4 Getting Started
- 2.5 Baseboard Preparation
- 2.5.1 Configuring the Hardware
- 2.5.2 Setting Switches and Jumpers
- 2.5.3 J6, Bus Mode Selection
- 2.5.4 J9, Standalone Operating Mode
- 2.5.5 J10, Flash Bank Selection
- 2.5.6 J15, +/-12 V Present Header
- 2.5.7 J20, Safe Start Header
- 2.5.8 J25, SROM Initialization Enable Header
- 2.5.9 J99, Flash Bank A Programming Enable Header
- 2.5.10 SW2, Geographic Address
- 2.6 Operating Modes
- 2.7 Installing Hardware
- 2.8 Connecting to a Console Port
- 2.9 Applying Power
- Controls, LEDs, and Connectors
- 3.1 Overview
- 3.2 Board Layout
- 3.3 Front Panel Connectors and LEDs
- 3.4 ABORT/Reset Switch
- 3.5 On-Board Connectors and Headers
- 3.5.1 J19, Front Panel Asynchronous Serial Port
- 3.5.2 J95, Front Panel 10/100/1000 Megabits/s Ethernet Connector
- 3.5.3 CompactPCI J1/J2 Connectors
- 3.5.4 CompactPCI Bus Connector
- 3.5.5 CompactPCI Bus Connector
- 3.5.6 CompactPCI User I/O Connector
- 3.5.7 CompactPCI Connector
- 3.5.8 CompactPCI User I/O Connector
- 3.5.9 PCI Mezzanine Card (PMC) Connectors
- 3.5.10 Boundary Scan JTAG Header
- 3.5.11 Processor JTAG/COP Header
- 3.5.12 Stand-Alone Operation Select Header
- 3.5.13 Flash Boot Bank Select Header
- 3.5.14 Safe Start Header
- 3.5.15 Bus Mode Select Header
- 3.5.16 SROM Initialization Enable Header
- 3.5.17 Flash Bank A Write Protect Header
- 3.5.18 +/-12 V Present Header
- Functional Description
- 4.1 Overview
- 4.2 Block Diagram
- 4.3 General Description
- 4.3.1 Processor Bus Resources
- 4.3.2 Processor
- 4.3.3 L3 Cache
- 4.3.4 MV64360 System Controller
- 4.3.4.1 MV64360 CPU Bus Interface
- 4.3.4.2 MV64360 DDR SDRAM Interface
- 4.3.4.3 MV64360 32-bit Interface to Devices
- 4.3.4.4 MV64360 Dual PCI/PCI-X Interfaces
- 4.3.4.5 MV64360 Integrated Gigabit Ethernet MACs
- 4.3.4.6 MV64360 Integrated 2 Megabit SRAM
- 4.3.4.7 MV64360 General-Purpose 32-bit Timer/Counters
- 4.3.4.8 MV64360 Watchdog Timer
- 4.3.4.9 MV64360 I2O Message Unit
- 4.3.4.10 MV64360 Four-Channel Independent DMA Controller
- 4.3.4.11 MV64360 I2C Interface
- 4.3.4.12 Interrupt Controller
- 4.3.4.13 PCI Bus Arbitration
- 4.3.4.14 Board Reset Logic
- 4.3.4.15 MV64360 MPP Configuration
- 4.3.4.16 MV64360 Reset Configuration
- 4.3.5 System Memory
- 4.3.6 Flash Memory
- 4.3.7 NVRAM, Real-Time Clock, Watchdog Timer
- 4.3.8 TL16C550C UART Devices
- 4.3.9 System Registers
- 4.3.10 Serial EEPROM Devices
- 4.3.11 PCI Bus 0.0
- 4.3.12 PCI Bus 1.0
- 4.3.13 IDE Controller
- 4.3.14 Intel 21555 PCI-to-PCI Bridge
- 4.3.15 CompactPCI Bus
- 4.3.16 PMC Slots
- 4.4 Miscellaneous
- 5 Transition Module Preparation and Installation
- 5.1 Overview
- 5.2 Block Diagram
- 5.3 Preparing the Transition Module
- 5.4 Rear Panel Connectors
- 5.5 On-Board Connectors and Headers
- 5.6 Jumper Settings
- 5.7 Functional Description
- 5.7.1 IDE Flash
- 5.7.2 Ethernet Interface (CompactPCI Version)
- 5.7.3 Hot-Swap Support
- 5.7.4 Serial EEPROM
- 5.7.5 PMC I/O Modules
- 5.7.6 Asynchronous Serial Ports
- 5.7.7 PMC I/O Module
- 5.7.8 PMC I/O Module Form Factor
- 5.7.9 PMC I/O Connector
- 5.7.10 Host I/O Connector
- 5.7.11 PMC I/O Module Presence Detection and Identification
- 5.8 Installing the PIM
- 5.9 Installing the Transition Module
- 5.10 Removing the Transition Module in a Hot-Swap Chassis
- Remote Start via the PCI Bus
- MOTLoad Firmware
- Memory Maps
- A Related Documentation
- Index