Motorola MC68VZ328 User Manual
Motorola Hardware
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Table of contents
Document Outline
- Title Page
- Contact Information
- Table of Contents
- List of Figures
- List of Tables
- List of Examples
- About This Book
- Chapter1 Introduction
- 1.1 Features of the MC68VZ328
- 1.2 CPU
- 1.3 Modules of the MC68VZ328
- 1.3.1 Memory Controller
- 1.3.2 Clock Generation Module and Power Control Module
- 1.3.3 System Control
- 1.3.4 Chip-Select Logic
- 1.3.5 DRAM Controller
- 1.3.6 LCD Controller
- 1.3.7 Interrupt Controller
- 1.3.8 General-Purpose I/O (GPIO) Lines
- 1.3.9 Real-Time Clock
- 1.3.10 General-Purpose Timer
- 1.3.11 Serial Peripheral Interfaces (SPI)
- 1.3.12 Universal Asynchronous Receiver/Transmitter (UART) Modules
- 1.3.13 Pulse-Width Modulators (PWM)
- 1.3.14 In-Circuit Emulation Module
- 1.3.15 Bootstrap Mode
- Chapter2 Signal Descriptions
- 2.1 Signals Grouped by Function
- 2.2 Power and Ground Signals
- 2.3 Clock and System Control Signals
- 2.4 Address Bus Signals
- 2.5 Data Bus Signals
- 2.6 Bus Control Signals
- 2.7 Interrupt Controller Signals
- 2.8 LCD Controller Signals
- 2.9 UART 1 and UART 2 Controller Signals
- 2.10 Timer Signals
- 2.11 Pulse-Width Modulator Signals
- 2.12 Serial Peripheral Interface 1 Signals
- 2.13 Serial Peripheral Interface 2 Signals
- 2.14 Chip-Select and EDO RAM Interface Signals
- 2.15 SDRAM Interface Signals
- 2.16 In-Circuit Emulation (ICE) Signals
- Chapter3 Memory Map
- Chapter4 Clock Generation Module and Power Control Module
- Chapter5 System Control
- Chapter6 Chip-Select Logic
- Chapter7 DRAM Controller
- Chapter8 LCD Controller
- 8.1 LCD Controller Features
- 8.2 LCD Controller Operation
- 8.3 Programming Model
- 8.3.1 LCD Screen Starting Address Register
- 8.3.2 LCD Virtual Page Width Register
- 8.3.3 LCD Screen Width Register
- 8.3.4 LCD Screen Height Register
- 8.3.5 LCD Cursor X Position Register
- 8.3.6 LCD Cursor Y Position Register
- 8.3.7 LCD Cursor Width and Height Register
- 8.3.8 LCD Blink Control Register
- 8.3.9 LCD Panel Interface Configuration Register
- 8.3.10 LCD Polarity Configuration Register
- 8.3.11 LACD Rate Control Register
- 8.3.12 LCD Pixel Clock Divider Register
- 8.3.13 LCD Clocking Control Register
- 8.3.14 LCD Refresh Rate Adjustment Register
- 8.3.15 LCD Panning Offset Register
- 8.3.16 LCD Frame Rate Control Modulation Register
- 8.3.17 LCD Gray Palette Mapping Register
- 8.3.18 PWM Contrast Control Register
- 8.3.19 Refresh Mode Control Register
- 8.3.20 DMA Control Register
- 8.4 Programming Example
- Chapter9 Interrupt Controller
- Chapter10 I/O Ports
- 10.1 Port Configuration
- 10.2 Status of I/O Ports During Reset
- 10.3 I/O Port Operation
- 10.4 Programming Model
- 10.4.1 Port A Registers
- 10.4.2 Port B Registers
- 10.4.3 Port C Registers
- 10.4.4 Port D Operation
- 10.4.5 Port D Registers
- 10.4.5.1 Port D Direction Register
- 10.4.5.2 Port D Data Register
- 10.4.5.3 Port D Interrupt Options
- 10.4.5.4 Port D Pull-up Enable Register
- 10.4.5.5 Port D Select Register
- 10.4.5.6 Port D Polarity Register
- 10.4.5.7 Port D Interrupt Request Enable Register
- 10.4.5.8 Port D Keyboard Enable Register
- 10.4.5.9 Port D Interrupt Request Edge Register
- 10.4.6 Port E Registers
- 10.4.7 Port F Registers
- 10.4.8 Port G Registers
- 10.4.9 Port J Registers
- 10.4.10 Port K Registers
- 10.4.11 Port M Registers
- Chapter11 Real-Time Clock
- Chapter12 General-Purpose Timers
- Chapter13 Serial Peripheral Interface 1 and 2
- Chapter14 Universal Asynchronous Receiver/Transmitter 1 and 2
- 14.1 Introduction to the UARTs
- 14.2 Serial Operation
- 14.3 UART Operation
- 14.4 Programming Model
- 14.4.1 UART 1 Status/Control Register
- 14.4.2 UART 1 Baud Control Register
- 14.4.3 UART 1 Receiver Register
- 14.4.4 UART 1 Transmitter Register
- 14.4.5 UART 1 Miscellaneous Register
- 14.4.6 UART 1 Non-Integer Prescaler Register
- 14.4.7 Non-Integer Prescaler Programming Example
- 14.4.8 UART 2 Status/Control Register
- 14.4.9 UART 2 Baud Control Register
- 14.4.10 UART 2 Receiver Register
- 14.4.11 UART 2 Transmitter Register
- 14.4.12 UART 2 Miscellaneous Register
- 14.4.13 UART 2 Non-Integer Prescaler Register
- 14.4.14 FIFO Level Marker Interrupt Register
- Chapter15 Pulse-Width Modulator 1 and 2
- Chapter16 In-Circuit Emulation
- Chapter17 Bootstrap Mode
- 17.1 Bootstrap Mode Operation
- 17.2 Bootloader Flowchart
- 17.3 Special Notes
- Chapter18 Application Guide
- Chapter19 Electrical Characteristics
- 19.1 Maximum Ratings
- 19.2 DC Electrical Characteristics
- 19.3 AC Electrical Characteristics
- 19.3.1 CLKO Reference to Chip-Select Signals Timing
- 19.3.2 Chip-Select Read Cycle Timing
- 19.3.3 Chip-Select Write Cycle Timing
- 19.3.4 Chip-Select Flash Write Cycle Timing
- 19.3.5 Chip-Select Timing Trim
- 19.3.6 DRAM Read Cycle 16-Bit Access (CPU Bus Master)
- 19.3.7 DRAM Write Cycle 16-Bit Access (CPU Bus Master)
- 19.3.8 DRAM Hidden Refresh Cycle (Normal Mode)
- 19.3.9 DRAM Hidden Refresh Cycle (Low-Power Mode)
- 19.3.10 LCD SRAM/ROM DMA Cycle 16-Bit Mode Access (1 Wait State)
- 19.3.11 LCD DRAM DMA Cycle 16-Bit EDO RAM Mode Access (LCD Bus Master)
- 19.3.12 LCD DRAM DMA Cycle 16-Bit Fast Page Mode Access (LCD Bus Master)
- 19.3.13 LCD Controller Timing
- 19.3.14 Page-Miss SDRAM CPU Read Cycle (CAS Latency=1)
- 19.3.15 Page-Hit SDRAM CPU Read Cycle (CAS Latency=1)
- 19.3.16 Page-Hit CPU Read Cycle for 8-Bit SDRAM (CAS Latency=1)
- 19.3.17 Page-Miss SDRAM CPU Write Cycle (CAS Latency=1)
- 19.3.18 Page-Hit SDRAM CPU Write Cycle (CAS Latency=1)
- 19.3.19 Page-Hit CPU Byte-Write Cycle for 8-Bit SDRAM (CAS Latency=1)
- 19.3.20 Page-Hit CPU Read Cycle in Power-down Mode (CAS Latency=1, Bit APEN of SDRAM Power-down...
- 19.3.21 Exit Self-Refresh Due to CPU Read Cycle (CAS Latency=1, Bit RM of DRAM Control Register...
- 19.3.22 Enter Self-Refresh Due to No Activity for 64 Clocks (Bit RM of DRAM Control Register=1)
- 19.3.23 Page-Miss at Starting of LCD DMA for SDRAM (CAS Latency=1)
- 19.3.24 Page-Miss at Start and in Middle of LCD DMA (CAS Latency=1)
- 19.3.25 Page-Hit LCD DMA Cycle for SDRAM (CAS Latency=1)
- 19.3.26 SPI 1 and SPI 2 Generic Timing
- 19.3.27 SPI 1 Master Using DATA_READY Edge Trigger
- 19.3.28 SPI 1 Master Using DATA_READY Level Trigger
- 19.3.29 SPI 1 Master “Don’t Care” DATA_READY
- 19.3.30 SPI 1 Slave FIFO Advanced by Bit Count
- 19.3.31 SPI 1 Slave FIFO Advanced by SS Rising Edge
- 19.3.32 Normal Mode Timing
- 19.3.33 Emulation Mode Timing
- 19.3.34 Bootstrap Mode Timing
- Chapter20 Mechanical Data and Ordering Information
- Index