C.10 v5r1 additions – Intel AS/400 RISC Server User Manual

Page 354

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16500

29300-37400

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890-2488 (1587)

84100-108900

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10000

29300-37400

24 - 32

1.41 MB*

1300

890-2488 (1585)

84100-108900

12900-16700

4550

29300-37400

24 - 32

1.41 MB*

1300

890-2488 (1583)

84100-108900

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2000

29300-37400

24 - 32

1.41 MB*

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890-2488 (1581)

84100-108900

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1050

29300-37400

24 - 32

1.41 MB*

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890-2488 (1579)

84100-108900

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560

29300-37400

24 - 32

1.41 MB*

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890-2488 (1578)

84100-108900

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240

29300-37400

24 - 32

1.41 MB*

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890-2488 (1577)

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29300-37400

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1.41 MB*

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MCU

Processor

CIW

Interactive

CPW

Processor CPW

CPU

Range

L2 cache

per CPU

Chip Speed

MHz

Model

Table C.9.2.1 Standard Models 8xx Servers

* 890 Models share L2 cache between 2 processors

Other models available in V5R2 and listed in C.10 V5R1 Additions are as follows:
y

All 270 Models

y

All 820 Models

y

Model 830-2400

y

All 840 model listed in Table C.10.4.1.1 V5R1 Capacity Upgrade on-demand Models

C.10 V5R1 Additions

In V5R1 the following new iSeries models were introduced:
y

820 and 840 server models

y

270 server models

y

270 and 820 Dedicated servers for Domino

y

840 Capacity Upgrade on-demand models (including V4R5 models December 2000)

See Chapter 2, iSeries RISC Server Model Performance Behavior, for a description of the performance
highlights of the new Dedicated Servers for Domino (DSD) models.

IBM i 6.1 Performance Capabilities Reference - January/April/October 2008

©

Copyright IBM Corp. 2008

Appendix C CPW, CIW and MCU for System i Platform

354

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