Jameco Electronics Rabbit 3000 - Manual (Page 265)

256 Rabbit 3000 Microprocessor
SLA r 4 fr * * L * r = {r[6,0],0}; CY = r[7]
SRA (HL) 10 f b * * L * (HL) = {(HL)[7],(HL)[7,1]};
CY = (HL)[0]
SRA (IX+d) 13 f b * * L * (IX+d) = {(IX+d)[7],
(IX+d)[7,1]}; CY = (IX+d)[0]
SRA (IY+d) 13 f b * * L * (IY+d) = {(IY+d)[7],
(IY+d)[7,1]}; CY = (IY+d)[0]
SRA r 4 fr * * L * r = {r[7],r[7,1]}; CY = r[0]
SRL (HL) 10 f b * * L * (HL) = {0,(HL)[7,1]};
CY = (HL)[0]
SRL (IX+d) 13 f b * * L * (IX+d) = {0,(IX+d)[7,1]};
CY = (IX+d)[0]
SRL (IY+d) 13 f b * * L * (IY+d) = {0,(IY+d)[7,1]};
CY = (IY+d)[0]
SRL r 4 fr * * L * r = {0,r[7,1]};
CY = r[0]
19.15 Instruction Prefixes
Instruction clk A I S Z V C Operation
ALTD 2 - - - - alternate register destinatIn
for next Instruction
IOE 2 - - - - I/O external prefix
IOI 2 - - - - I/O internal prefix
19.16 Block Move Instructions
Instruction clk A I S Z V C Operation
LDD 10 d - - * - (DE) = (HL); BC = BC-1;
DE = DE-1; HL = HL-1
LDDR 6+7i d - - * - if {BC != 0} repeat:
LDI 10 d - - * - (DE) = (HL); BC = BC-1;
DE = DE+1; HL = HL+1
LDIR 6+7i d - - * - if {BC != 0} repeat:
If any of the block move instructions are prefixed by an I/O prefix, the destination will be
in the specified I/O space. Add 1 clock for each iteration for the prefix if the prefix is IOI
(internal I/O). If the prefix is IOE, add 2 clocks plus the number of I/O wait states enabled.
The V flag is set when BC transitions from 1 to 0. If the V flag is not set another step is
performed for the repeating versions of the instructions. Interrupts can occur between dif-
ferent repeats, but not within an iteration equivalent to LDD or LDI. Return from the inter-
rupt is to the first byte of the instruction which is the I/O prefix byte if there is one.
A new LDIR/LDDR bug was discovered in September, 2002. The problem has to do with
wait states and the block move operations. With this problem, the first iteration of
LDIR/LDDR uses the correct number of wait states for both the read and the write. How-
ever, all subsequent iterations use the number of waits programmed for the memory
located at the write address for both the read and the write cycles. This becomes a problem
when moving a block of data from a slow memory device requiring wait states to a fast
memory device requiring no wait states. With respect to external I/O operations, the
LDIR
or LDDR performs reads with zero wait states independent of the waits programmed for the
I/O for all but the first iteration. The first iteration is correct. This bug is automatically cor-
rected by Dynamic C, and will be fixed in future generations of the chip.