Samsung S3F80JB - Manual (Page 10)

S3F80JB MICROCONTROLLER xi
List of Figures
(Continued)
Figure Title Page
Number Number
5-1 S3C8/S3F8-Series Interrupt Types........................................................................... 5-2
5-2 S3F80JB Interrupt Structure..................................................................................... 5-4
5-3 ROM Vector Address Area ....................................................................................... 5-5
5-4 Interrupt Function Diagram....................................................................................... 5-8
5-5 System Mode Register (SYM) .................................................................................. 5-10
5-6 Interrupt Mask Register (IMR) .................................................................................. 5-11
5-7 Interrupt Request Priority Groups ............................................................................. 5-12
5-8 Interrupt Priority Register (IPR) ................................................................................ 5-13
5-9 Interrupt Request Register (IRQ).............................................................................. 5-14
6-1
System Flags Register (FLAGS) .............................................................................. 6-6
7-1
Main Oscillator Circuit (External Crystal or Ceramic Resonator) ............................ 7-1
7-2 External Clock Circuit ............................................................................................... 7-1
7-3 System Clock Circuit Diagram.................................................................................. 7-2
7-4 System Clock Control Register (CLKCON)............................................................... 7-3
8-1
RESET Sources of The S3F80JB............................................................................. 8-2
8-2 RESET Block Diagram of The S3F80JB .................................................................. 8-3
8-3 RESET Block Diagram by LVD for The S3F80JB IN STOP MODE .......................... 8-4
8-4 Internal Power-On Reset Circuit ............................................................................... 8-5
8-5 Timing Diagram for Internal Power-On Reset Circuit................................................ 8-6
8-6 Reset Timing Diagram for The S3F80JB in STOP mode by IPOR ........................... 8-7
8-7 Block Diagram for Back-up Mode ............................................................................. 8-10
8-8 Timing Diagram for Back-up Mode Input and Released by LVD............................... 8-10
9-1
S3F80JB I/O Port Data Register Format .................................................................. 9-5
9-2 Pull-up Resistor Enable Registers (Port 0 and Port 2 only) ...................................... 9-6
10-1
Basic Timer Control Register (BTCON) .................................................................... 10-2
10-2 Timer 0 Control Register (T0CON) ........................................................................... 10-5
10-3 Timer 0 DATA Register (T0DATA) ........................................................................... 10-5
10-4 Simplified Timer 0 Function Diagram: Interval Timer Mode ...................................... 10-6
10-5 Simplified Timer 0 Function Diagram: PWM Mode ................................................... 10-7
10-6 Simplified Timer 0 Function Diagram: Capture Mode ............................................... 10-8
10-7 Basic Timer and Timer 0 Block Diagram .................................................................. 10-9
11-1
Simplified Timer 1 Function Diagram: Capture Mode ............................................... 11-2
11-2 Simplified Timer 1 Function Diagram: Interval Timer Mode ...................................... 11-3
11-3 Timer 1 Block Diagram ............................................................................................. 11-4
11-4 Timer 1 Control Register (T1CON) ........................................................................... 11-5
11-5 Timer 1 Registers (T1CNTH, T1CNTL, T1DATAH, T1DATAL)................................. 11-6