P4conl – Samsung S3F80JB User Manual
Page 103
CONTROL REGISTERS
S3F80JB
4-36
P4CONL
—
Port 4 Control Register (Low Byte)
E3H Set1 Bank1
Bit
Identifier
.7 .6 .5 .4 .3 .2 .1 .0
Reset Value
1 1 1 1 1 1 1 1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode
Register addressing mode only
.7 and .6
P4.3 Mode Selection Bits
0 0
C-MOS
input
mode
0 1
Open-drain
output
mode
1 0
Push-pull
output
mode
1
1
C-MOS input with pull up mode
.5 and .4
P4.2 Mode Selection Bits
0 0
C-MOS
input
mode
0 1
Open-drain
output
mode
1 0
Push-pull
output
mode
1
1
C-MOS input with pull up mode
.3 and .2
P4.1 Mode Selection Bits
0 0
C-MOS
input
mode
0 1
Open-drain
output
mode
1 0
Push-pull
output
mode
1
1
C-MOS input with pull up mode
.1 and .0
P4.0 Mode Selection Bits
0 0
C-MOS
input
mode
0 1
Open-drain
output
mode
1 0
Push-pull
output
mode
1
1
C-MOS input with pull up mode
NOTE: After CPU reset, P4.3 – P4.0 will be C-MOS input with pull up mode by the reset value of P4CONL register.