Samsung S3F80JB - Manual (Page 231)

S3F80JB RESET
8-13
SED&R (Stop Error Detect and Recovery)
The Stop Error Detect & Recovery circuit is used to release stop mode and prevent abnormal - stop mode that
can be occurred by battery bouncing. It executes two functions in related to the internal logic of P0 and P2.4-P2.7.
One is releasing from stop status by switching the level of input port (P0 or P2.4-P2.7) and the other is keeping
the chip from the stop mode when the chip is in abnormal status.
— Releasing from stop mode
When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’, if falling edge input signal enters in
through Port0 or P2.4-P2.7, S3F80JB is released stop mode and generate reset signal. On the other hand,
when IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘1’, S3F80JB is only released stop mode.
Reset doesn’t occur. When the falling edge of a pin on Port0 and P2.4-P2.7 is entered, the chip is released
from stop mode even though external interrupt is disabled.
— Keeping the chip from entering abnormal - stop mode
This circuit detects the abnormal status by checking the port (P0 and P2.4-P2.7) status. If the chip is in
abnormal status it keeps from entering stop mode.
NOTE
In case of P2.0-2.3, SED&R circuit isn’t implemented. So although 4pins, P2.0-2.3, have the falling edge input
signal in stop mode, if external interrupt is disabled, the stop state of S3F80JB is unchanged. Do not use stop
mode if you are using an external clock source because Xin input must be cleared internally to VSS to reduce
current leakage.