2 block diagram – LG GSA-4167B User Manual

Page 57

Advertising
background image

1.2 Block Diagram

61

Data

WPLL

ADIP

Detector

Detector

Counter

PRML

PLL

Generator

Demodulate

Servo

CD-ROM
Decoder

DVD

PI-ECU

DVD

PO-ECU

DRAM

MCIF

ATAPI

AUDIO

DRAM

Interface

Clock

Generator

Test

Control

VINP

VINN

REXT

PTEST [2:0]

IP1LPPIN

IP2MIRR

LOWZB

IDGATE

RFHLD

W1LPF[2:0]

ADC

ADC

ADIPVRT

LPP

Wobble

WOBSIG

Jitter

CD-DSP

CAV

AUDIO

NRZI,NRZIB

LVDS

DCLK,DCLKB

WGATEB

WRGATE2

SRFH

WRSTOP

Sample

Hold

WBLSH
MPDSH

WFPDSH

RFPDSH

CD-ROM

CD

Encoder

Modulator

DAC

ADC

FE
PE

TE

LPSA

FOD

DAVC

TRD

XCI

TRST(NMI)

TCK(SCK)

TDI(SCI)

TDO(SCO)

TMS

XCO

Serial I/F

SDATA

RFDEN

SCLK

WDEN
LDBUSY

FEMCK

TEST[3:0]

MRSTB

TESTB[1:2]

ROUT
DOUT

LOUT

DVD

Descramble

DVD

Scramble

Auth

BCA

SSEQ

MSEQ

RA[12.10:0]

DWE

RD[15:0]

DRAS
DCAS

RAMCL

DQMU
DQML

DACKB

CS3FXB

DREQ

CS1FXB
PDIAGB

DASPB

DA2

IOCS16B

IORDY

ZIOWB

HINTRQ

HRSTB

ZIORB

DATA [15:0]

DA1
DA0

SFG

ATZC

DERECT

BLANK

EFG

LED

LNDTRK

LDD

TLD

TCSHSPBLV

DCKE

W2LPF[2:0]

H8S

CPU

ADC

GAD1

ADGATEB

INT0B

FOK

CPWRB
CPRDB

UCS2B

A[20:0]

CPU[15:0]

INT1B
INT2B

UCS0B
GPIO05(UCS1B)
CPRDB
CPWRB

A[20:1]

CPU[15:0]

GPIO06(CSEL)

GPIO07(HEATRUN)

ICUIN6(EJECTSW)

ICUIN7(ACTFLG)

GPIO04(A[0])

SDRAM
16Mbit

ZCS

UCS3B

INT3B

SRFL

TCPH

TIBH

BCENT

FAD0(VRDC2N)

TVDP

TVDN

ADC

WAI T

ICUIN8(LOADIN)

DAC

SIGM

SPD

ADIPINP

ADIPVR1

Cmp

Advertising
This manual is related to the following products: