Texas Instruments TMS320DM357 User Manual
User's guide
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Table of contents
Document Outline
- Table of Contents
- Preface
- 1 Introduction
- 2 Peripheral Architecture
- 3 USB Controller Host and Peripheral Modes Operation
- 3.1 USB Controller Peripheral Mode Operation
- 3.2 USB Controller Host Mode Operation
- 3.3 DMA Operation
- 3.4 Interrupt Handling
- 3.5 Test Modes
- 3.6 Reset Considerations
- 3.7 Interrupt Support
- 3.8 EDMA Event Support
- 3.9 Power Management
- 4 Registers
- 4.1 Control Register (CTRLR)
- 4.2 Status Register (STATR)
- 4.3 RNDIS Register (RNDISR)
- 4.4 Auto Request Register (AUTOREQ)
- 4.5 USB Interrupt Source Register (INTSRCR)
- 4.6 USB Interrupt Source Set Register (INTSETR)
- 4.7 USB Interrupt Source Clear Register (INTCLRR)
- 4.8 USB Interrupt Mask Register (INTMSKR)
- 4.9 USB Interrupt Mask Set Register (INTMSKSETR)
- 4.10 USB Interrupt Mask Clear Register (INTMSKCLRR)
- 4.11 USB Interrupt Source Masked Register (INTMASKEDR)
- 4.12 USB End of Interrupt Register (EOIR)
- 4.13 USB Interrupt Vector Register (INTVECTR)
- 4.14 Transmit CPPI Control Register (TCPPICR)
- 4.15 Transmit CPPI Teardown Register (TCPPITDR)
- 4.16 CPPI DMA End of Interrupt Register (CPPIEOIR)
- 4.17 Transmit CPPI Masked Status Register (TCPPIMSKSR)
- 4.18 Transmit CPPI Raw Status Register (TCPPIRAWSR)
- 4.19 Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR)
- 4.20 Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR)
- 4.21 Receive CPPI Control Register (RCPPICR)
- 4.22 Receive CPPI Masked Status Register (RCPPIMSKSR)
- 4.23 Receive CPPI Raw Status Register (RCPPIRAWSR)
- 4.24 Receive CPPI Interrupt Enable Set Register (RCPPIENSETR)
- 4.25 Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR)
- 4.26 Receive Buffer Count 0 Register (RBUFCNT0)
- 4.27 Receive Buffer Count 1 Register (RBUFCNT1)
- 4.28 Receive Buffer Count 2 Register (RBUFCNT2)
- 4.29 Receive Buffer Count 3 Register (RBUFCNT3)
- 4.30 Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0)
- 4.31 Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1)
- 4.32 Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2)
- 4.33 Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3)
- 4.34 Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4)
- 4.35 Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5)
- 4.36 Transmit CPPI Completion Pointer (TCPPICOMPPTR)
- 4.37 Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0)
- 4.38 Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1)
- 4.39 Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2)
- 4.40 Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3)
- 4.41 Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4)
- 4.42 Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5)
- 4.43 Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6)
- 4.44 Receive CPPI Completion Pointer (RCPPICOMPPTR)
- 4.45 Function Address Register (FADDR)
- 4.46 Power Management Register (POWER)
- 4.47 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX)
- 4.48 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX)
- 4.49 Interrupt Enable Register for INTRTX (INTRTXE)
- 4.50 Interrupt Enable Register for INTRRX (INTRRXE)
- 4.51 Interrupt Register for Common USB Interrupts (INTRUSB)
- 4.52 Interrupt Enable Register for INTRUSB (INTRUSBE)
- 4.53 Frame Number Register (FRAME)
- 4.54 Index Register for Selecting the Endpoint Status and Control Registers (INDEX)
- 4.55 Register to Enable the USB 2.0 Test Modes (TESTMODE)
- 4.56 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP)
- 4.57 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0)
- 4.58 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0)
- 4.59 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR)
- 4.60 Control Status Register for Host Transmit Endpoint (HOST_TXCSR)
- 4.61 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP)
- 4.62 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR)
- 4.63 Control Status Register for Host Receive Endpoint (HOST_RXCSR)
- 4.64 Count 0 Register (COUNT0)
- 4.65 Receive Count Register (RXCOUNT)
- 4.66 Type Register (Host mode only) (HOST_TYPE0)
- 4.67 Transmit Type Register (Host mode only) (HOST_TXTYPE)
- 4.68 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0)
- 4.69 Transmit Interval Register (Host mode only) (HOST_TXINTERVAL)
- 4.70 Receive Type Register (Host mode only) (HOST_RXTYPE)
- 4.71 Receive Interval Register (Host mode only) (HOST_RXINTERVAL)
- 4.72 Configuration Data Register (CONFIGDATA)
- 4.73 Transmit and Receive FIFO Register for Endpoint 0 (FIFO0)
- 4.74 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1)
- 4.75 Transmit and Receive FIFO Register for Endpoint 2 (FIFO2)
- 4.76 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3)
- 4.77 Transmit and Receive FIFO Register for Endpoint 4 (FIFO4)
- 4.78 OTG Device Control Register (DEVCTL)
- 4.79 Transmit Endpoint FIFO Size (TXFIFOSZ)
- 4.80 Receive Endpoint FIFO Size (RXFIFOSZ)
- 4.81 Transmit Endpoint FIFO Address (TXFIFOADDR)
- 4.82 Receive Endpoint FIFO Address (RXFIFOADDR)
- 4.83 Transmit Function Address (TXFUNCADDR)
- 4.84 Transmit Hub Address (TXHUBADDR)
- 4.85 Transmit Hub Port (TXHUBPORT)
- 4.86 Receive Function Address (RXFUNCADDR)
- 4.87 Receive Hub Address (RXHUBADDR)
- 4.88 Receive Hub Port (RXHUBPORT)
- Appendix A Revision History