Xilinx IP Ethernet AVB Endpoint v2.4 UG492 User Manual
Logicore, Ip ethernet avb endpoint v2.4
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Table of contents
Document Outline
- LogiCORETM IP Ethernet AVB Endpoint v2.4
- Revision History
- Table of Contents
- Schedule of Figures
- Schedule of Tables
- About This Guide
- Introduction
- Licensing the Core
- Overview of Ethernet Audio Video Bridging
- Generating the Core
- Core Architecture
- Ethernet AVB Endpoint Transmission
- Ethernet AVB Endpoint Reception
- Real Time Clock and Time Stamping
- Precise Timing Protocol Packet Buffers
- Configuration and Status
- Constraining the Core
- System Integration
- Software Drivers
- Quick Start Example Design
- Detailed Example Design (Standard Format)
- Directory and File Contents
- <project directory>
- <project directory>/<component name>
- <component name>/doc
- <component name>/example design
- <component name>/implement
- implement/results
- <component name>/simulation
- simulation/functional
- simulation/timing
- <component_name>/drivers/v2_04_a
- drivers/avb_v2_04_a/data
- drivers/avb_v2_04_a/examples
- drivers/avb_v2_04_a/src
- Implementation Scripts
- Simulation Scripts
- Example Design
- Directory and File Contents
- Detailed Example Design (EDK format)
- Directory and File Contents
- <project directory>
- <project directory>/<component name>
- <component name>/doc
- <component name>/MyProcessorIPLib
- MyProcessorIPLib/pcores/eth_avb_endpoint_v2_04_a
- pcores/eth_avb_endpoint_v2_04_a/data
- pcores/eth_avb_endpoint_v2_04_a/hdl/vhdl
- pcores/eth_avb_endpoint_v2_04_a/netlist
- MyProcessorIPLib/drivers/avb_v2_04_a
- drivers/avb_v2_04_a/data
- drivers/avb_v2_04_a/examples
- drivers/avb_v2_04_a/src
- Importing the Ethernet AVB Endpoint Core into the Embedded Development Kit (EDK)
- Directory and File Contents
- RTC Time Stamp Accuracy