56 l0 instruction cache data msr (l0_ic_data_msr), 00001713h, 00000000_00000000h – AMD Geode LX [email protected] User Manual
Page 154: 00001714h, L0 instruction cache data msr (l0_ic_data_msr), Xxxxxxxx_xxxxxxxxh, 00001715h, 00000000_xxxxxxxxh
154
AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions
33234H
5.5.2.55 Instruction Cache Tag with Increment (IC_TAG_I_MSR)
5.5.2.56 L0 Instruction Cache Data MSR (L0_IC_DATA_MSR)
5.5.2.57 L0 Instruction Cache Tag with Increment MSR (L0_IC_TAG_I_MSR)
MSR Address
00001713h
Type
R/W
Reset Value
00000000_00000000h
IC_TAG_I_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
LRU
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TAG
RSVD
V
IC_TAG_I_MSR Bit Descriptions
Bit
Name
Description
63:0
---
Definition same as Instruction Cache Tag MSR (MSR 00001712h). Except read/write
of this register causes an auto-increment on the IC_INDEX_MSR (MSR 00001710h).
MSR Address
00001714h
Type
RO
Reset Value
xxxxxxxx_xxxxxxxxh
L0_IC_DATA_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
DATA (Upper)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DATA (Lower)
L0_IC_DATA_MSR Bit Descriptions
Bits
Name
Description
63:0
DATA
QWORD Read from L0 Cache. The address to the QWORD specified by the LINE field
from IC_INDEX_MSR (MSR 00001710h[4:0]).
MSR Address
00001715h
Type
RO
Reset Value
00000000_xxxxxxxxh
L0_IC_TAG_I_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TLB_NUM
RSVD
TAG
LINE
RSVD
V