AMD Geode LX 800@0.9W - Manual (Page 190)

190 AMD Geode™ LX Processors Data Book
CPU Core Register Descriptions 33234H
5.5.2.100 L2 Cache Tag with Increment MSR (L2_TAG_I_MSR)
The L2_TAG_I_MSR has the auto incremented L2 cache tag, MRU and valid bits for diagnostic accesses.
Bit descriptions for this register are the same as for L2_TAG_MSR (MSR 00001924h), except read/write of this register
causes an auto increment on the L2_INDEX_MSR (MSR 00001922h).
5.5.2.101 L2 Cache Built-In Self-Test MSR (L2_BIST_MSR)
L2_BIST_MSR has the L2 cache index for diagnostic accesses.
MSR Address 00001925h
Type R/W
Reset Value 00000000_00000000h
L2_TAG_I_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L2_TAG RSVD L2_MRU RSVD
L2_V
A
L
ID
MSR Address 00001926h
Type R/W
Reset Value 00000000_00000000h
L2_BIST_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
BIST_MR
U
_GO
BIST_DATA_CMP_STAT
BIST_D
A
T
A_GO
BIST_T
A
G
_G
O_CMP
B
IST
_T
A
G
_GO_W
A
Y3
B
IST
_T
A
G
_GO_W
A
Y2
B
IST
_T
A
G
_GO_W
A
Y1
B
IST
_T
A
G
_GO_W
A
Y0
BIST_T
A
G
_GO
BIST
_MR
U
_DR
T
_EN
BIST_MR
U
_EN
BIST_D
A
T
A_DR
T_EN
BIST_D
A
T
A_EN
B
IST
_T
A
G
_DR
T
_EN
B
IST
_T
A
G
_EN
L2_BIST_MSR Bit Descriptions
Bit Name Description
63:30 RSVD (RO) Reserved (Read Only). (Default = 0)
29 BIST_MRU_GO
(RO) L2 Cache Most Recently Used BIST Result (Read Only).
0: Fail. (Default)
1: Pass.
28:13 BIST_DATA_
CMP_STAT (RO) L2 Cache Data BIST Result (Read Only). One for each passed comparator - 16
total. (Default = 0)
12 BIST_DATA_GO
(RO) L2 Cache Data BIST Result (Read Only).
0: Fail. (Default)
1: Pass.
11 BIST_TAG_GO_
CMP (RO) L2 Cache Tag Comparator BIST Result (Read Only).
0: Fail. (Default)
1: Pass.