4 gld error msr (gld_msr_error), Gld error msr (gld_msr_error) – AMD Geode LX [email protected] User Manual
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AMD Geode™ LX Processors Data Book
Display Controller Register Descriptions
33234H
6.6.1.4
GLD Error MSR (GLD_MSR_ERROR)
9
GFXIOW_MSK
Graphics Controller Register Write SMI. When set to 1, disables generation of the
SMI that indicates that one or more of the VGA’s Graphics Controller registers has
been written.
8
SEQIOR_MSK
Sequencer Register Read SMI. When set to 1, disables generation of the SMI that
indicates that one or more of the VGA’s Sequencer registers has been read.
7
SEQIOW_MSK
Sequencer Register Write SMI. When set to 1, disables generation of the SMI that
indicates that one or more of the VGA’s Sequencer registers has been written.
6
CRTCIOR_MSK
CRTC Register Read SMI. When set to 1, disables generation of the SMI that indi-
cates that one or more of the VGA’s CRTC registers has been read; writing a 1 to this
bit clears it.
5
CRTCIOW_MSK
CRTC Register Write SMI. When set to 1, disables generation of the SMI that indi-
cates that one or more of the VGA’s CRTC registers has been written.
4
CRTCIO_MSK
CRTC Invalid Register I/O SMI Mask. When set to 1, disables generation of a syn-
chronous SMI when a non-implemented VGA CRT Controller Register is read or writ-
ten.
3
VGA_BL_MSK
VGA Vertical Blank SMI Mask. When set to 1, disables generation of the VGA Vertical
Blank SMI.
2
ISR0_MSK
Input Status Register 0 SMI Mask. When set to 1, disables generation of the VGA
Input Status Register SMI.
1
MISC_MSK
Miscellaneous Output Register SMI Mask. When set to 1, disables generation of the
Miscellaneous Output Register synchronous SMI.
0
VG_BL_MSK
DC Vertical Blank SMI Mask. When set to 1, disables the DC Vertical Blank SMI when
set to 1.
MSR Address
80002003h
Type
R/W
Reset Value
00000000_00000000h
GLD_MSR_SMI Bit Descriptions (Continued)
Bit
Name
Description
GLD_MSR_ERROR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
C
W
D
_
CHECK_ERR
SYNCB
UF
_ERR
DF
IFO_ERR
SMI_ER
R
ADDR
_ERR
TYPE_ERR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
CWD_CH
ECK_MASK
S
Y
N
C
B
U
F_MASK
DFIF
O_
E
R
R_MASK
SMI_ERR_
MA
SK
ADDR_ER
R_MASK
TYPE_ERR_MASK