AMD Geode LX 800@0.9W - Manual (Page 496)

496 AMD Geode™ LX Processors Data Book
Video Input Port Register Descriptions 33234H
6.10.2.7 VIP Task A Video Even Base Address (VIP_TASK_A_VID_EVEN_BASE)
6.10.2.8 VIP Task A Video Odd Base Address (VIP_TASK_A_VID_ODD_BASE)
VIP Memory Offset 18h
Type
R/W
Reset Value 00000000h
VIP_TASK_A_VID_EVEN_BASE Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TASK_A_VIDEO_EVEN_BASE_ADDRESS Program to 00000
VIP_TASK_A_VID_EVEN_BASE Bit Descriptions
Bit Name Description
31:0 TASK_A
VIDEO_EVEN
BASE Task A Video Even Base Address. This register specifies the base address in graphics
memory where Task A even video field data will be stored. Changes to this register take
effect at the beginning of the next field. This value needs to be 32-byte aligned. (Bits [4:0]
are required to be 00000.)
Note: This register is double buffered. When a new value is written to this register, the
new value is placed in a special pending register, and the Base Register Not
Updated bit (VIP Memory Offset 08h[16]) is set to 1. The Task A Video Data
Even Base Address register is not updated at this point. When the first data of
the next field is captured, the pending values of all base registers are written to
the appropriate base registers, and the Base Register Not Updated bit is cleared.
VIP Memory Offset 1Ch
Type
R/W
Reset Value 00000000h
VIP_TASK_A_VID_ODD_BASE Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TASK_A_VIDEO_ODD_BASE Program to 00000
VIP_TASK_A_VID_ODD_BASE Bit Descriptions
Bit Name Description
31:0 TASK_A_VIDE
O_ODD_BASE Task A Video Odd Base Address. This register specifies the base address in graphics
memory where Task A odd video field data will be stored. Changes to this register take
effect at the beginning of the next field. This value needs to be 32-byte aligned. (Bits [4:0]
are required to be 00000.)
Note: This register is double buffered. When a new value is written to this register, the
new value is placed in a special pending register, and the Base Register Not
Updated bit (VIP Memory Offset 08h[16]) is set to 1. The Task A Video Data Odd
Base Address Register is not updated at this point. When the first data of the
next field is captured, the pending values of all base registers are written to the
appropriate base registers, and the Base Register Not Updated bit is cleared.