AMD Geode LX 800@0.9W - Manual (Page 506)

506 AMD Geode™ LX Processors Data Book
Video Input Port Register Descriptions 33234H
6.10.2.25 VIP Page Offset/ Page Count (VIP_PAGE_OFFSET )
6.10.2.26 VIP Vertical Start/Stop (VIP_VERT_START_STOP )
VIP Memory Offset 68h
Type
R/W
Reset Value 00000000h
VIP_PAGE_OFFSET Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAGE_OFFSET Program to 00000
VIP_PAGE_OFFSET Bit Descriptions
Bit Name Description
31:0 PAGE_OFFSET Page Offset. This register specifies the offset to the next page of buffer data. If the page
count is 2 or greater, the next frame of data is started at an address of buffer +
PAGE_OFFSET. Up to eight pages (frames) can be accumulated. The address of the
next frame is located at a “Page Offset” address. Note that ancillary data and MSG/
STRM data is not paged. This only applies to video and VBI data. The value in this regis-
ter needs to be 32-byte aligned. (Bits [4:0] are required to be 00000.)
VIP Memory Offset 6Ch
Type
R/W
Reset Value 00000000h
VIP_VERT_START_STOP Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD VERT_END RSVD VERT_START
VIP_VERT_START_STOP Bit Description
Bit Name Description
31:28 RSVD Reserved. Set to 0.
27:16 VERT_END Vertical End Capture. This register specifies the last line # in a field/frame that is cap-
tured when the subwindow capture function is enabled in non BT.601 modes. In BT.601
interlaced modes, this register determines when the odd field line capture completes. In
601 non-interlaced modes, this register determines when the video capture completes.
See Figure 6-48 "BT.601 Mode Vertical Timing" on page 473 for additional detail.
15:12 RSVD Reserved. Set to 0.
11:0 VERT_START Vertical Start Capture. This register specifies the first line # in a field/frame that is cap-
tured when the subwindow capture function is enabled in non 601 modes. In BT.601
interlaced modes, this register determines when the odd field video capture starts. In
BT.601 non-interlaced modes, this register determines when the video capture starts.
See Figure 6-48 "BT.601 Mode Vertical Timing" on page 473 for additional detail.