4 companion device interface, 1 gio_gliu, 2 gio_sync – AMD Geode LX [email protected] User Manual

Page 536: 3 gio_pci, Figure 6-56, Processor clock generation

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536

AMD Geode™ LX Processors Data Book

GeodeLink™ Control Processor

33234H

Figure 6-56. Processor Clock Generation

6.13.4

Companion Device Interface

The AMD Geode companion device interface for I/O con-
nections (GIO) provides the system interface between the
AMD Geode CS5536 companion device and the
AMD Geode LX processor. The GIO supports companion
device modes for current and future companion device
needs. The major blocks (shown in Figure 6-57 on page
537)
of the GIO are:

GIO_GLIU

GIO_SYNC

GIO_PCI

Features

CS5536 companion device support:

— Supports CPU Interface Serial (CIS) that mux'es

signals: INPUT_DISABLE, OUTPUT_DISABLE and
Legacy (LGCY) signals: A20M, INIT, SUSP, NMI,
INTR, SMI.

— System interface signals clocked on raw PCI input

clock.

• No master capabilities.

6.13.4.1

GIO_GLIU

The GIO_GLIU interface module is responsible for all the
GLIU slave functionality. The GIO_GLIU slave implements
a large MSR space consisting of the required standard
GLIU device MSRs and the MSR controls for the I/O com-
panion modes and the Legacy signals. The GIO_GLIU
must properly decode all possible GLIU transaction types
including the unexpected addresses, request types and
sizes, and must return the proper number of responses. In
addition, it provides error logic to detect unexpected
addresses and types and implements the processor float-
ing point exception handling logic.

6.13.4.2

GIO_SYNC

The GIO synchronization module, GIO_SYNC, handles
synchronization of all signals that cross from the GLIU to
PCI domain or PCI to GLIU domain.

6.13.4.3

GIO_PCI

The GIO_PCI module drives the values of the system inter-
face signals. Table 6-83 on page 537 shows the source of
each output signal in each of the AMD Geode companion
device modes.

SYSPLL

DOTPLL

DOTREF

SYSREF

GLCP_DOTPLL[15]

GLCP_SYS_RSTPLL[12]

SDRAM Clocks

GL Clocks

DOTCLK

PCI

CPU Core

GLCP_SYS_RSTPLL[11]

Dividers

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