AMD Geode LX 800@0.9W - Manual (Page 551)

AMD Geode™ LX Processors Data Book 551
GeodeLink™ Control Processor Register Descriptions 33234H
6.14.2.9 GLCP Clock Control (GLCP_CLKOFF)
This register has bits that, when set, force clocks off using GeodeLink™ Clock Control (GLCC) logic in the system. This is
for debugging only, and should not be used for power management.
MSR Address 4C000010h
Type R/W
Reset Value 00000000_00000000h
GLCP_CLKOFF Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
VIPVIP
VIPG
LI
U
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES
AESG
LIU
A
ESEE
GLCPDBG GL
CP
GLI
U
GLCPPCI
VPV
OP
VPDO
T
_2
VPDO
T
_1
VPDO
T
_0
VPGLIU_1 VPGLIU_0
PCIPCIF
PC
IP
C
I
PCIGLIU GLIU1_1 GLIU1_0
DCGLIU_1 DCGLIU_0
RSVD
D
CDO
T
_
0
GLIU0_1 GLIU0_0
GP
GLMC DRAM
BC_GLIUS
BC
_
V
A
MSS IPIPE
FPUF
AST
FPU
S
L
O
W
GLCP_CLKOFF Bit Descriptions
Bit Name Description
63:34 RSVD Reserved.
33 VIPVIP VIP VIPCLK Off. When set, disables VIP VIPCLK.
32 VIPGLIU VIP GLIU Clock Off. When set, disables VIP GLIU clock.
31 AES AES Core Functional Clock Off. When set, disables AES encryption/decryption
clock.
30 AESGLIU AES GLIU Clock Off. When set, disables AES GLIU interface clock.
29 AESEE AES EEPROM Clock Off. When set, disables AES EEPROM clock.
28 GLCPDBG GLCP Debug Clock Off. When set, disables GLCP DBG logic clock.
27 GLCPGLIU GLCP GLIU Clock Off. When set, disables GLCP GLIU clock.
26 GLCPPCI GLCP GIO PCI Clock Off. When set, disables GLCP’s GIO PCI clock.
25 VPVOP VP VOP Clock Off. When set, disables VOP logic clock.
24 VPDOT_2 VP DOT Clock 2 Off. When set, disables VP Dot Clock 2 (vp_vid).
23 VPDOT_1 VP Dot Clock 1 Off. When set, disables VP Dot Clock 1 (lcd_pix).
22 VPDOT_0 VP Dot Clock 0 Off. When set, disables VP Dot Clock 0 (vp_pix).
21 VPGLIU_1 VP GLIU Clock 1 Off. When set, disables VP GLIU Clock 1 (lcd).
20 VPGLIU_0 VP GLIU Clock 0 Off. When set, disables VP GLIU Clock 0 (vp).
19 PCIPCIF Fast PCI Clock Off. When set, disables fast PCI clock inside GLPCI block.
18 PCIPCI PCI Clock Off. When set, disables normal PCI clock inside GLPCI block.
17 PCIGLIU GLPCI Clock Off. When set, disables clock entering GLPCI block.
16 GLIU1_1 GLIU1 Clock Off. When set, disables main clock to secondary GLIU.
15 GLIU1_0 GLIU1 Timer Logic Clock Off. When set, disables clock to timer logic of secondary
GLIU.
14 DCGLIU_1 DC GLIU Clock 1 Off. When set, disables DC GLIU Clock 1 (VGA).
13 DCGLIU_0 DC GLIU Clock 0 Off. When set, disables DC GLIU Clock 0 (DC).
12 RSVD Reserved. Unused bit, reads what was written, value written has no effect.