AMD Geode LX 800@0.9W - Manual (Page 648)

648 AMD Geode™ LX Processors Data Book
Instruction Set 33234H
8.3.4.3 MOV - Move to/from Test Registers
Operation
IF (CPL <> 0) THEN
#GP(0);
ELSE
DEST <= SRC;
Description
The above forms of the MOV instruction store the contents of a test register (either TR0, TR1, TR2, TR3, TR4, TR5, TR6,
or TR7) to a general purpose register (either EAX, ECX, EDX, EBX, ESP, EBP, ESI, or EDI), or load a test register from a
general purpose register.
Thirty-two bit operands are always used with these instructions, regardless of the operand size attribute.
Flags Affected
None.
Exceptions
#GP(0) If the current privilege level is not 0.
Notes
These are not the Intel or AMD Geode LX processor test registers. Writing to a test register has no side effects. Reading
from a test register has no side effects.
The reg field within the ModR/M byte specifies which of the test registers is involved. Reg values of 0, 1, 2, 3, 4, 5, 6, 7
specify TR0, TR1, TR2, TR3, TR4, TR5, TR6, and TR7 respectively. The two bits in the mod field are always 11. The r/m
field specifies the general register involved.
Moving a value into a test register has no side effects.
Software other than DMI handlers should not use test registers, because DMI handlers might not preserve the contents of
test registers. DMI handlers may use test registers as a place for saving and restoring general registers when the state of
the stack is unknown.
Opcode Instruction Clocks Description
0F 24 /r MOV r32,tr 1 Move test register to general register
0F 26 /r MOV tr, r32 2 Move general register to test register