ARM Cortex R4F User Manual
Cortex, R4 and cortex-r4f, Technical reference manual
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Table of contents
Document Outline
- Cortex-R4 and Cortex-R4F Technical Reference Manual
- Contents
- List of Tables
- List of Figures
- Preface
- Introduction
- 1.1 About the processor
- 1.2 About the architecture
- 1.3 Components of the processor
- 1.4 External interfaces of the processor
- 1.5 Power management
- 1.6 Configurable options
- 1.7 Execution pipeline stages
- 1.8 Redundant core comparison
- 1.9 Test features
- 1.10 Product documentation, design flow, and architecture
- 1.11 Product revision information
- Programmer’s Model
- 2.1 About the programmer’s model
- 2.2 Instruction set states
- 2.3 Operating modes
- 2.4 Data types
- 2.5 Memory formats
- 2.6 Registers
- 2.7 Program status registers
- 2.8 Exceptions
- 2.9 Acceleration of execution environments
- 2.10 Unaligned and mixed-endian data access support
- 2.11 Big-endian instruction support
- Processor Initialization, Resets, and Clocking
- System Control Coprocessor
- 4.1 About the system control coprocessor
- 4.2 System control coprocessor registers
- 4.2.1 Register allocation
- 4.2.2 c0, Main ID Register
- 4.2.3 c0, Cache Type Register
- 4.2.4 c0, TCM Type Register
- 4.2.5 c0, MPU Type Register
- 4.2.6 c0, Multiprocessor ID Register
- 4.2.7 The Processor Feature Registers
- 4.2.8 c0, Debug Feature Register 0
- 4.2.9 c0, Auxiliary Feature Register 0
- 4.2.10 Memory Model Feature Registers
- 4.2.11 Instruction Set Attributes Registers
- 4.2.12 c0, Current Cache Size Identification Register
- 4.2.13 c0, Current Cache Level ID Register
- 4.2.14 c0, Cache Size Selection Register
- 4.2.15 c1, System Control Register
- 4.2.16 Auxiliary Control Registers
- 4.2.17 c1, Coprocessor Access Register
- 4.2.18 Fault Status and Address Registers
- 4.2.19 c6, MPU memory region programming registers
- 4.2.20 Cache operations
- 4.2.21 c9, BTCM Region Register
- 4.2.22 c9, ATCM Region Register
- 4.2.23 c9, TCM Selection Register
- 4.2.24 c11, Slave Port Control Register
- 4.2.25 c13, FCSE PID Register
- 4.2.26 c13, Context ID Register
- 4.2.27 c13, Thread and Process ID Registers
- 4.2.28 Validation Registers
- 4.2.29 Correctable Fault Location Register
- 4.2.30 Build Options Registers
- Prefetch Unit
- Events and Performance Monitor
- 6.1 About the events
- 6.2 About the PMU
- 6.3 Performance monitoring registers
- 6.3.1 c9, Performance Monitor Control Register
- 6.3.2 c9, Count Enable Set Register
- 6.3.3 c9, Count Enable Clear Register
- 6.3.4 c9, Overflow Flag Status Register
- 6.3.5 c9, Software Increment Register
- 6.3.6 c9, Performance Counter Selection Register
- 6.3.7 c9, Cycle Count Register
- 6.3.8 c9, Event Selection Register
- 6.3.9 c9, Performance Monitor Count Registers
- 6.3.10 c9, User Enable Register
- 6.3.11 c9, Interrupt Enable Set Register
- 6.3.12 c9, Interrupt Enable Clear Register
- 6.4 Event bus interface
- Memory Protection Unit
- Level One Memory System
- Level Two Interface
- Power Control
- Debug
- 11.1 Debug systems
- 11.2 About the debug unit
- 11.3 Debug register interface
- 11.4 Debug register descriptions
- 11.4.1 Accessing debug registers
- 11.4.2 CP14 c0, Debug ID Register
- 11.4.3 CP14 c0, Debug ROM Address Register
- 11.4.4 CP14 c0, Debug Self Address Offset Register
- 11.4.5 CP14 c1, Debug Status and Control Register
- 11.4.6 Data Transfer Register
- 11.4.7 Watchpoint Fault Address Register
- 11.4.8 Vector Catch Register
- 11.4.9 Debug State Cache Control Register
- 11.4.10 Instruction Transfer Register
- 11.4.11 Debug Run Control Register
- 11.4.12 Breakpoint Value Registers
- 11.4.13 Breakpoint Control Registers
- 11.4.14 Watchpoint Value Registers
- 11.4.15 Watchpoint Control Registers
- 11.4.16 Operating System Lock Status Register
- 11.4.17 Authentication Status Register
- 11.4.18 Device Power-down and Reset Control Register
- 11.4.19 Device Power-down and Reset Status Register
- 11.5 Management registers
- 11.6 Debug events
- 11.7 Debug exception
- 11.8 Debug state
- 11.8.1 Entering debug state
- 11.8.2 Behavior of the PC and CPSR in debug state
- 11.8.3 Executing instructions in debug state
- 11.8.4 Writing to the CPSR in debug state
- 11.8.5 Privilege
- 11.8.6 Accessing registers and memory
- 11.8.7 Coprocessor instructions
- 11.8.8 Effect of debug state on non-invasive debug
- 11.8.9 Effects of debug events on processor registers
- 11.8.10 Exceptions in debug state
- 11.8.11 Leaving debug state
- 11.9 Cache debug
- 11.10 External debug interface
- 11.11 Using the debug functionality
- 11.12 Debugging systems with energy management capabilities
- FPU Programmer’s Model
- Integration Test Registers
- Cycle Timings and Interlock Behavior
- 14.1 About cycle timings and interlock behavior
- 14.2 Register interlock examples
- 14.3 Data processing instructions
- 14.4 QADD, QDADD, QSUB, and QDSUB instructions
- 14.5 Media data-processing
- 14.6 Sum of Absolute Differences (SAD)
- 14.7 Multiplies
- 14.8 Divide
- 14.9 Branches
- 14.10 Processor state updating instructions
- 14.11 Single load and store instructions
- 14.12 Load and Store Double instructions
- 14.13 Load and Store Multiple instructions
- 14.14 RFE and SRS instructions
- 14.15 Synchronization instructions
- 14.16 Coprocessor instructions
- 14.17 SVC, BKPT, Undefined, and Prefetch Aborted instructions
- 14.18 Miscellaneous instructions
- 14.19 Floating-point register transfer instructions
- 14.20 Floating-point load/store instructions
- 14.21 Floating-point single-precision data processing instructions
- 14.22 Floating-point double-precision data processing instructions
- 14.23 Dual issue
- AC Characteristics
- Processor Signal Descriptions
- A.1 About the processor signal descriptions
- A.2 Global signals
- A.3 Configuration signals
- A.4 Interrupt signals, including VIC interface signals
- A.5 L2 interface signals
- A.6 TCM interface signals
- A.7 Dual core interface signals
- A.8 Debug interface signals
- A.9 ETM interface signals
- A.10 Test signals
- A.11 MBIST signals
- A.12 Validation signals
- A.13 FPU signals
- ECC Schemes
- Revisions
- Glossary