AMD Athlon 27493 - Manual (Page 97)

26237C—May 2003 AMD Athlon™ XP Processor Model 10 Data Sheet
Preliminary Information
Appendix B - Conventions and Abbreviations 85
Appendix B
Conventions and
Abbreviations
This section contains information about the conventions and
abbreviations used in this document.
Signals and Bits
■
Active-Low Signals—Signal names containing a pound sign,
such as SFILL#, indicate active-Low signals. They are
asserted in their Low-voltage state and negated in their
High-voltage state. When used in this context, High and Low
are written with an initial upper case letter.
■ Signal Ranges—In a range of signals, the highest and lowest
signal numbers are contained in brackets and separated by a
colon (for example, D[63:0]).
■
Reserved Bits and Signals—Signals or bus bits marked
reserved must be driven inactive or left unconnected, as
indicated in the signal descriptions. These bits and signals
are reserved by AMD for future implementations. When
software reads registers with reserved bits, the reserved bits
must be masked. When software writes such registers, it
must first read the register and change only the
non-reserved bits before writing back to the register.
■ Three-State—In timing diagrams, signal ranges that are
high impedance are shown as a straight horizontal line
half-way between the high and low levels.
■ Invalid and Don’t-Care—In timing diagrams, signal ranges
that are invalid or don't-care are filled with a screen pattern.