Agilent Technologies DC152 - Manual (Page 29)

3.2.5. Bandwidth and Rise Time
The bandwidth specification indicates the frequency at which an input signal will be attenuated by 3 dB
(approximately 30% loss of amplitude). The bandwidth also affects the minimum rise and fall times that can be
passed through the front-end electronics. A pulse with a very sharp edge will be observed to have a minimum rise
time (τ
min
) determined by the front-end electronics. In general a pulse with a given 10-90% rise time (τ
10-90real
) will be
observed with a slower value given by:
τ
10-90
2 =
τ
10-90real
2 +
τ
min
2 where
τ
min
(ns) ≈ 0.35 (GHz-ns) / BW (GHz)
For the HZ option in 1 M Ω coupling the 700 MHz Bandwidth Limiter cannot be used. Furthermore, for FS gain >
5V the 200 MHz Bandwidth Limiter is always active.
3.2.6. Input Voltage and Offset
The input channel provides a fully programmable amplifier with variable input voltage and offset. Full Scale (FS)
input voltages are selectable in a 1, 2, 5 sequence for the range shown above. Care should be taken to select an input
voltage range that will allow the signal to be recorded using as much dynamic range of the digitizer as possible. The
Variable Offset is programmable in the range of ±2 V when using an FS Input Voltage setting of 500 mV or below,
increasing to ± Maximum Offset for FS settings above 500 mV (see the preceding table). The raw 10-bit ADC data
values are read as 16-bit integers in the range [-32768, +32704] with nominal steps of 64 LSB’s between successive
codes and the first and last values reserved for underflow and overflow respectively. The midpoint value, 0, of the
range corresponds to the negative of the offset voltage. Thus the Full Scale Range (FSR) goes from
–Offset Voltage – (FS/2) to –Offset Voltage + (FS/2)
Signals going outside of the FSR will be clipped and data values for the clipped portion of a signal should be
regarded as erroneous.
3.2.7. Vertical Resolution
The digitizers described in this manual use an ADC system with 10 bits of vertical resolution (1024 levels). The
dynamic range of the ADC covers the Full Scale Range (FSR) of the Input Voltage setting. For example, if the Input
Voltage is set to 1 V then the ADC resolution is equivalent to 0.977 mV. To obtain the best dynamic range from the
ADC care should be taken to ensure that the input signal varies over more than 50% of the Input Voltage FSR
setting.
3.2.8. DC Accuracy and Linearity
These 10-bit digitizers use low noise front-end electronics in order to ensure voltage measurement is made with
accuracy and precision. DC voltage accuracy, at 0 V offset, is better than ±2% (±1% typical) of the input voltage full
scale. The static differential nonlinearity is < 2 LSB. The integral linearity is good to ± 1 LSB (typical).
3.2.9. Using Probes
The 50 Ω and 1 MΩ input impedance settings make it possible to use Acqiris digitizers with a wide variety of
probes. The 50 Ω setting is most commonly used for active probes and low impedance (500 Ω) passive probes. The
1 M Ω setting is normally used for high impedance probes. While it is possible to use a variety of different
manufacturers high impedance probes we recommend the use of our model P001 Passive Probe. The model P001 is
matched to the Acqiris digitizers to ensure that effects that can reduce measurement quality, such as bandwidth loss
and capacitive loading, are minimized. The P001 features 300 MHz bandwidth, 10 M
Ω input impedance and 10:1
attenuation. These specifications make it an excellent choice for most general purpose probing applications. Before
using any Passive Probe with a digitizer care should be taken to check that the probe has been correctly adjusted
(refer to the Probe’s Calibration procedure).
NOTE: Passive high impedance probes are not suitable for high fidelity measurements above 100 MHz. The non-
negligible (5-10 pF) tip capacitance loads the signal causing distortion and/or ringing when combined with the
ground lead inductance.
User Manual: Family of 10-bit Digitizers Page 29 of 55