Cypress Perform CY7C1513KV18 - Manual (Page 31)

Document Number: 001-00435 Rev. *E Revised March 30, 2009 Page 31 of 31
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.
CY7C1511KV18, CY7C1526KV18
CY7C1513KV18, CY7C1515KV18
© Cypress Semiconductor Corporation, 2005-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
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Products
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Clocks & Buffers clocks.cypress.com
Wireless wireless.cypress.com
Memories memory.cypress.com
Image Sensors image.cypress.com
PSoC Solutions
General psoc.cypress.com/solutions
Low Power/Low Voltage psoc.cypress.com/low-power
Precision Analog psoc.cypress.com/precision-analog
LCD Drive psoc.cypress.com/lcd-drive
CAN 2.0b psoc.cypress.com/can
USB psoc.cypress.com/usb
Document History Page
Document Title: CY7C1511KV18/CY7C1526KV18/CY7C1513KV18/CY7C1515KV18, 72-Mbit QDR™-II SRAM 4-Word
Burst Architecture
Document Number: 001-00435
Rev. ECN No.
Orig. of
Change
Submission
Date
Description of change
** 374703 SYT See ECN New Data Sheet
*A 1103823 NXR See ECN Updated I
DD
spec
Updated ordering information table
*B 1699083 VKN/AESA See ECN Converted from Advance Information to Preliminary
*C 2148307 VKN/AESA See ECN Changed PLL lock time from 1024 cycles to 20 μs
Added footnote #21 related to I
DD
Corrected typo in the footnote #25
*D 2606839 VKN/PYRS 11/13/08 Changed JTAG ID [31:29] from 001 to 000,
Updated power up sequence waveform and its description,
Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to
“–55°C to +125°C” in the “Maximum Ratings” on page 21,
Included Thermal Resistance values,
Changed the package size from 15 x 17 x 1.4 mm to 13 x 15 x 1.4 mm.
*E 2681899 VKN/PYRS 04/01/2009 Converted from preliminary to final
Added note on top of the Ordering Information table
Moved to external web
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