Sharp MZ-3500 - Manual (Page 17)

2) Memory mapper (MMR) SP6102R-001 signal description
MZ3500
Pin No.
10
12
Polarity
Signal Name
ST
DO
0 7
A15
A13
IN/OUT
IN
IN/OUT
IN
Function
Main CPU DRAM output buffer (LS244) switching strap.
Bidirectional main CPU data bus.
(Data bus 0 7)
Main CPU address bus.
Used in the memory mapping logic of the MMR for address output for the DRAM, ROM, and
shared RAM. (Address bus 13 ~ 15)
13 A1 IN
Main CPU address bus.
Used in the I/O port select logic of the MMR to assign device number
14 SRES OUT
Sub-CPU bus request signal.
• After power on: Halts the sub-CPU.
• After write command (LDA-80H: OUT#FD) by the main CPU- Starts the sub-CPU.
This signal is issued after transfer of the main CPU program contained m the ROM-IPL.
(Sub CPU Reset)
15 SRQ OUT
Sub-CPU bus request signal.
• After power on: Resets bus request to sub-CPU.
• After write command (LDA-02H: OUT#FC) by the main CPU: Place bus request to the sub-CPU
This signal is issued to bus of the sub-CPU, after the main CPU writes to the shared RAM a command
parameter to the sub-CPU or reads the message status from the sub-CPU.
(Sob CPU Request)
16
18
AR13
AR15
OUT
Address signal to the main CPU dynamic RAM.
The main CPU addresssignals.A13-A 15, merged in the memory mapping logic circuit to produce
AR13-AR15. This is means by which the 4 basic and CP/M memory maps are made, along with MSI
and MSO.
19 R32 OUT
BASIC interpreter 32KB mask ROM chip select signal.
Valid when SD2 is active (Sharp ROM based BASIC). Command ILDA 02H OUT 3F D)
(ROM 32K select)
20
21
lOAB
SRDY
IN
Internal MMR I/O port select logic signal.
Goes low by the command IN/OUT #FC-#FF.
(Input/Output Address)
IN
Input of ready signal from the sub-CPU.
(Sub CPU Ready)
22 ROPB OUT
Chip select signal issued from the main CPU to the 8KB mask ROM.
Valid with SDO active (initialize state).
(ROM ipl)
23
26
ROAB
RODB
OUT
Chip select signal for four chip BASIC interpreter 8KB EPROM (A. B, C, D).
Valid with SD2 active (Sharp ROM based BASIC).
•R32B (alternate choice with the 32KB mask ROM chip select signal).
(ROM A~D Buffer)
27
30
31
RSAB
RSDB
OUT
Row address select signal for the main CPU dynamic RAM (block A-block D).
RAS (ROW ADDRESS SELECT; LINE ADDRESS SELECT) SIGNAL
(Row address Select)
SACK IN
Input of bus acknowledge signal from the sub-CPU.
When the mam CPU must write a command in the shared RAM a bus request is issued first, then the
command is written in the shared RAM after acknowledgement from the sub-CPU
I At the end of the command cycle bus request is released and the sub CPU executes the command
20-