Sharp MZ-3500 - Manual (Page 55)

5-7, Precompensate Circuit
M 7.3500
< I T E D A T A
PSO PS1 FM MFM Value of LSI63
0 0 Not changed Not changed 1101
0 1 - LATE(125ps) 1100
1 0 - EARLY(125iis) 1110
1 - - -
(Table 1)
WDAT.A.
8MHz
CLOCK
_r
lJnJljn_riJn_rL-rLr
EAKLY-
NOMAL-
LATE-
(Fig. 3)
The precompensate circuit is used to compensate the peak
shift before writing.
The FDC sends out the compensation rate to PSO and PS1
and the data bit location is shifted according to this signal.
With issuance of WDATA, the value dependent on PSO and
PS1 is set in the LS163. (See Table 1.) For instance, when
both PSO and PS1 are low, it will set "1101(D)" to the
LSI63, counted up by the 8 MHz clock, and QB is sent out
When it becomes "1110, 1111". When in EARLY (PS0=
"H", PS1="L”), the value "1110(E)" will be set to the
LSI 63 so that the output is issued 125ns earier than "not
changed". The QB output, however, will be supplied for a
period of two clock cycles.
5-8. Media detection
Insertion of a media on the MFD is detected via the signal
INDEX from the MFD. Since it takes 200ms for the media
to make a full turn, "NO MEDIA" is detected signal
INDEX does not appear within 200ms.
Set the counter to 200ms.
(Actually, slightly longer than 200ms.)
Media is present. Media is not present.
5-9. Controls during read, write, seek, and re­
calibrate
Above operations are all controlled via the FDC.
1) Control during read and write
2) Control during seek and recalibration
SEEK (or RECALB)
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