Altera LVDS SERDES - Manual

Altera LVDS SERDES IP Core User Guide
2014.08.18
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The Altera LVDS SERDES IP Core configures the serializer/deserializer (SERDES) and dynamic phase
alignment (DPA) blocks. The IP core also supports LVDS channels placement, legality checks, and LVDS
channel-related rule checks.
The Altera LVDS SERDES IP core is only available for Arria
®
10 devices. For Arria V, Cyclone
®
V, and
Stratix
®
V devices, follow the steps in Migrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores on
page 25 to migrate your IP.
Related Information
• LVDS SERDES Transmitter/Receiver (ALTLVDS_TX and ALTLVDS_RX) Megafunctions User Guide
Features
You can configure the features of Altera LVDS SERDES IP core through the IP Parameter Editor in the
Quartus
®
II software. The Altera LVDS SERDES IP core feature includes the ALTLVDS_RX and
ALTLVDS_TX IP cores features supported in Stratix V devices, such as:
• Parameterizable data channel widths
• Parameterizable serializer/deserializer (SERDES) factors
• Registered input and output ports
• PLL control signals
• Dynamic phase alignment (DPA) mode
• Soft clock data recovery (CDR) mode
Functional Modes
This table lists the functional modes for the Altera LVDS SERDES IP core.
Table 1: Functional Modes for the Altera LVDS SERDES IP Core
Description Functional Mode
In this mode, the IP core configures the SERDES block as a serializer. A
PLL generates the fast clock (
fclk ) and load enable ( loaden ) signals.
TX
ISO
9001:2008
Registered
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