Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP User Manual
Altera Measuring instruments
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EMI_DDR_UG-3.0
Section I. DDR and DDR2 SDRAM Controllers with
ALTMEMPHY IP User Guide
External Memory Interface Handbook Volume 3
Document last updated for Altera Complete Design Suite version:
Document publication date:
11.0
June 2011
External Memory Interface Handbook Volume 3 Section I.
DDR and DDR2 SDRAM Controllers with ALTMEMPHY
IP User Guide
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This manual is related to the following products:
Table of contents
Document Outline
- External Memory Interface Handbook Volume 3 Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
- Contents
- 1. About This IP
- 2. Getting Started
- 3. Parameter Settings
- 4. Compiling and Simulating
- 5. Functional Description—ALTMEMPHY
- Block Description
- ALTMEMPHY Signals
- PHY-to-Controller Interfaces
- Using a Custom Controller
- Preliminary Steps
- Design Considerations
- Clocks and Resets
- Calibration Process Requirements
- Other Local Interface Requirements
- Address and Command Interfacing
- Handshake Mechanism Between Read Commands and Read Data
- Handshake Mechanism Between Write Commands and Write Data
- Partial Write Operations
- Using a Custom Controller with the TimeQuest Timing Analyzer
- 6. Functional Description— High-Performance Controller II
- 7. Latency
- 8. Timing Diagrams
- Additional Information