Altera Embedded Peripherals IP User Manual
Embedded peripheral ip user guide
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Table of contents
Document Outline
- Embedded Peripheral IP User Guide
- Contents
- Introduction
- SDRAM Controller Core
- Core Overview
- Functional Description
- Configuration
- Hardware Simulation Considerations
- Example Configurations
- Software Programming Model
- Clock, PLL and Timing Considerations
- Document Revision History
- Tri-State SDRAM
- Compact Flash Core
- Common Flash Interface Controller Core
- EPCS Serial Flash Controller Core
- JTAG UART Core
- UART Core
- 16550 UART
- Core Overview
- Feature Description
- Software Programming Model
- Document Revision History
- SPI Core
- Optrex 16207 LCD Controller Core
- PIO Core
- Avalon-ST Serial Peripheral Interface Core
- PCI Lite Core
- Core Overview
- Performance and Resource Utilization
- Functional Description
- PCI-Avalon Bridge Blocks
- Avalon-MM Ports
- Prefetchable Avalon-MM Master
- Non-Prefectchable Avalon-MM Master
- I/O Avalon-MM Master
- PCI Bus Access Slave
- Control Register Access (CRA) Avalon-MM Slave
- Master and Target Performance
- PCI-to-Avalon Address Translation
- Avalon-to-PCI Address Translation
- Avalon-To-PCI Read and Write Operation
- Ordering of Requests
- PCI Interrupt
- Configuration
- Simulation Considerations
- Document Revision History
- MDIO Core
- On-Chip FIFO Memory Core
- Core Overview
- Functional Description
- Configuration
- Software Programming Model
- Programming with the On-Chip FIFO Memory
- On-Chip FIFO Memory API
- altera_avalon_fifo_init()
- altera_avalon_fifo_read_status()
- altera_avalon_fifo_read_ienable()
- altera_avalon_fifo_read_almostfull()
- altera_avalon_fifo_read_almostempty()
- altera_avalon_fifo_read_event()
- altera_avalon_fifo_read_level()
- altera_avalon_fifo_clear_event()
- altera_avalon_fifo_write_ienable()
- altera_avalon_fifo_write_almostfull()
- altera_avalon_fifo_write_almostempty()
- altera_avalon_write_fifo()
- altera_avalon_write_other_info()
- altera_avalon_fifo_read_fifo()
- Document Revision History
- Avalon-ST Multi-Channel Shared Memory FIFO Core
- SPI Slave/JTAG to Avalon Master Bridge Cores
- Avalon-ST Bytes to Packets and Packets to Bytes Converter Cores
- Avalon Packets to Transactions Converter Core
- Scatter-Gather DMA Controller Core
- Core Overview
- Resource Usage and Performance
- Functional Description
- Parameters
- Simulation Considerations
- Software Programming Model
- Programming with SG-DMA Controller
- Data Structure
- SG-DMA API
- alt_avalon_sgdma_do_async_transfer()
- alt_avalon_sgdma_do_sync_transfer()
- alt_avalon_sgdma_construct_mem_to_mem_desc()
- alt_avalon_sgdma_construct_stream_to_mem_desc()
- alt_avalon_sgdma_construct_mem_to_stream_desc()
- alt_avalon_sgdma_check_descriptor_status()
- alt_avalon_sgdma_register_callback()
- alt_avalon_sgdma_start()
- alt_avalon_sgdma_stop()
- alt_avalon_sgdma_open()
- Document Revision History
- Altera Modular Scatter-Gather DMA
- DMA Controller Core
- Video Sync Generator and Pixel Converter Cores
- Interval Timer Core
- Mutex Core
- Mailbox Core
- Vectored Interrupt Controller Core
- Core Overview
- Functional Description
- Register Maps
- Parameters
- Altera HAL Software Programming Model
- Software Files
- Macros
- Data Structure
- VIC API
- Run-time Initialization
- Board Support Package
- altera_vic_driver.enable_preemption
- altera_vic_driver.enable_preemption_into_new_register_set
- altera_vic_driver.enable_preemption_rs_<n>
- altera_vic_driver.linker_section
- altera_vic_driver.<name>.vec_size
- altera_vic_driver.<name>.irq<n>_rrs
- altera_vic_driver.<name>.irq<n>_ril
- altera_vic_driver.<name>.irq<n>_rnmi
- Default Settings for RRS and RIL
- VIC BSP Design Rules for Altera Hal Implementation
- RTOS Considerations
- Document Revision History
- Avalon-ST JTAG Interface Core
- System ID Core
- Performance Counter Core
- PLL Cores
- Altera MSI to GIC Generator
- Altera Interrupt Latency Counter