Altera SCFIFO - Manual

SCFIFO and DCFIFO IP Cores User Guide
2014.12.17
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Altera provides FIFO functions through the parameterizable single-clock FIFO (SCFIFO) and dual-clock
FIFO (DCFIFO) megafunction IP cores The FIFO functions are mostly applied in data buffering
applications that comply with the first-in-first-out data flow in synchronous or asynchronous clock
domains.
The specific names of the IP cores are as follows:
• SCFIFO: single-clock FIFO
• DCFIFO: dual-clock FIFO (supports same port widths for input and output data)
• DCFIFO_MIXED_WIDTHS: dual-clock FIFO (supports different port widths for input and output
data)
Note: The term “DCFIFO” refers to both the DCFIFO and DCFIFO_MIXED_WIDTHS IP cores, unless
specified.
Configuration Methods
You can configure and build the FIFO IP cores with the following methods:
Table 1: Configuration Methods
Method Description
Using the FIFO parameter editor. Altera recommends using this method to build your
FIFO IP cores. It is an efficient way to configure and
build the FIFO IP cores. The FIFO parameter editor
provides options that you can easily use to
configure the FIFO IP cores.
Manually instantiating the FIFO IP cores. Use this method only if you are an expert user. This
method requires that you know the detailed specifi‐
cations of the IP cores. You must ensure that the
input and output ports used, and the parameter
values assigned are valid for the FIFO IP cores you
instantiate for your target device.
Related Information
Introduction to Altera IP Cores
Provides general information about the Quartus II Parameter Editor
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