Altera Triple Speed Ethernet MegaCore Function User Manual
Triple-speed ethernet megacore function, User guide
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Table of contents
Document Outline
- Triple-Speed Ethernet MegaCore Function User Guide
- Contents
- 1. About This MegaCore Function
- 2. Getting Started with Altera IP Cores
- 3. Parameter Settings
- 4. Functional Description
- 10/100/1000 Ethernet MAC
- 1000BASE-X/SGMII PCS With Optional Embedded PMA
- Altera IEEE 1588v2 Feature
- 5. Triple-Speed Ethernet with IEEE 1588v2 Design Example
- 6. Configuration Register Space
- MAC Configuration Register Space
- PCS Configuration Register Space
- Register Initialization
- 7. Interface Signals
- Interface Signals
- 10/100/1000 Ethernet MAC Signals
- 10/100/1000 Multiport Ethernet MAC Signals
- 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
- 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
- 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
- 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA
- IEEE 1588v2 RX Timestamp Signals
- IEEE 1588v2 TX Timestamp Signals
- IEEE 1588v2 TX Timestamp Request Signals
- IEEE 1588v2 TX Insert Control Timestamp Signals
- IEEE 1588v2 Time-of-Day (ToD) Clock Interface Signals
- IEEE 1588v2 PCS Phase Measurement Clock Signal
- IEEE 1588v2 PHY Path Delay Interface Signals
- 1000BASE-X/SGMII PCS Signals
- 1000BASE-X/SGMII PCS and PMA Signals
- Timing
- Interface Signals
- 8. Design Considerations
- 9. Timing Constraints
- 10. Testbench
- 11. Software Programming Interface
- A. Ethernet Frame Format
- B. Simulation Parameters
- C. Time-of-Day (ToD) Clock
- D. ToD Synchronizer
- E. Packet Classifier
- F. Additional Information