Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core - Manual

Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core
User Guide
2015.05.04
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The Altera IOPLL megafunction IP core allows you to configure the settings of Arria ® 10 I/O PLL.
Altera IOPLL IP core supports the following features:
• Supports six different clock feedback modes: direct, external feedback, normal, source synchronous,
zero delay buffer, and LVDS mode.
• Generates up to nine clock output signals for the Arria 10 device.
• Switches between two reference input clocks.
• Supports adjacent PLL (
adjpllin
) input to connect with an upstream PLL in PLL cascading mode.
• Generates the Memory Initialization File (.mif) and allows PLL dynamic reconfiguration.
• Supports PLL dynamic phase shift.
Related Information
• Introduction to Altera IP Cores
Provides more information about the Altera IP cores and the parameter editor.
• Operation Modes on page 8
• Output Clocks on page 8
• Reference Clock Switchover on page 9
• PLL-to-PLL Cascading on page 9
Device Family Support
The Altera IOPLL IP core only supports the Arria 10 device family.
Altera IOPLL IP Core Parameters
The Altera IOPLL IP core parameter editor appears in the PLL category of the IP Catalog.
Altera IOPLL IP Core Parameters - PLL Tab
Table 1: Altera IOPLL IP Core Parameters - PLL Tab
Parameter Legal Value Description
Device Family Arria 10 Specifies the device family.
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