Altera Double Data Rate I/O - Manual

Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT,
and ALTDDIO_BIDIR) IP Cores User Guide
2015.01.23
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The Altera ® ® DDR I/O megafunction IP cores configure the DDR I/O registers in APEX ™ II, Arria ®
series, Cyclone ® series, HardCopy ® series, and Stratix ® series devices.
You can also use these IP cores to implement DDR registers in the logic elements (LEs). In Arria GX,
Stratix series, HardCopy II, HardCopy Stratix, and APEX II devices, the DDR registers are implemented
in the I/O element (IOE). In Cyclone series devices, the IP cores automatically implement the DDR
registers in the LEs closest to the pin. The ALTDDIO_IN IP core implements the interface for DDR
inputs. The ALTDDIO_OUT IP core implements the interface for DDR outputs. The ALTDDIO_BIDIR
IP core implements the interface for bidirectional DDR inputs and outputs.
ALTDDIO Features
The ALTDDIO IP cores implement a DDR interface and offer the following additional features:
• The ALTDDIO_IN IP core receives data on both edges of the reference clock
• The ALTDDIO_OUT IP core transmits data on both edges of the reference clock
• The ALTDDIO_BIDIR IP core transmits and receives data on both edges of the reference clock
• Asynchronous clear and asynchronous set input options available
• Synchronous clear and synchronous set input options available for Arrix GX and Stratix series devices.
•
inclock
signal to sample the DDR input
•
outclock
signal to register the data output
• Clock enable signals
• Bidirectional port for the ALTDDIO_BIDIR IP core
• An output enable input for the ALTDDIO_OUT and ALTDDIO_BIDIR IP cores
ALTDDIO Common Applications
DDR registers capture and/or send data at twice the rate of the clock or data strobe to interface with a
memory device or other high-speed interface application in which the data is clocked at both edges of the
clock.
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