Altera POS-PHY Level 4 IP Core User Manual
User guide pos-phy level 4 ip core
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101 Innovation Drive
San Jose, CA 95134
UG-IPPOSPHY4
User Guide
POS-PHY Level 4 IP Core
Document last updated for Altera Complete Design Suite version:
Document publication date:
14.1
December 2014
DecemberPOS-PHY Level 4 IP Core User Guide
c
The POS-PHY Level 4 IP Core is scheduled for product obsolescence and discontinued
support as described in
. Therefore, Altera does not recommend use of this IP
in new designs. For more information about Altera’s current IP offering, refer to Altera’s
bsite.
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Table of contents
Document Outline
- DecemberPOS-PHY Level 4 IP Core User Guide
- 1. About This IP Core
- 2. Getting Started
- 3. Parameter Settings
- 4. Functional Description—Receiver
- Features
- Block Description
- Clock Structure
- Reset Structure
- Error Flagging and Handling
- Signals
- Avalon-MM Interface Register Map
- Latency Information
- 5. Functional Description—Transmitter
- Features
- Block Description
- Clock Structure
- Reset Structure
- Error Flagging and Handling
- Signals
- Avalon-MM Interface Register Map
- Latency Information
- 6. Testbench
- A. Start-Up Sequence
- B. Sharing PLLs for Multicore Designs
- C. Optimum Frequency for rxsys_clk
- D. Board Design
- E. Programming the SPI-4.2 Calendar via the Avalon Memory-Mapped Interface
- F. Static and Dynamic Phase Alignment
- G. Conversion from v2.2.x
- Additional Information