Altera RapidIO MegaCore Function User Manual
User guide rapidio megacore function
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101 Innovation Drive
San Jose, CA 95134
UG-MC_RIOPHY-4.1
User Guide
RapidIO MegaCore Function
Document last updated for Altera Complete Design Suite version:
Document publication date:
14.0 and 14.0 Arria 10 Edition
August 2014
RapidIO MegaCore Function v14.0 and v14.0 Arria 10
Edition User Guide
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Table of contents
Document Outline
- RapidIO MegaCore Function v14.0 and v14.0 Arria 10 Edition User Guide
- Contents
- 1. About This MegaCore Function
- 2. Getting Started
- Customizing and Generating IP Cores
- Files Generated for Altera IP Cores (Legacy Parameter Editor)
- Files Generated for Altera IP Cores
- Simulating IP Cores
- Integrating Your IP Core in Your Design
- Specifying Constraints
- Compiling the Full Design and Programming the FPGA
- Instantiating Multiple RapidIO IP Cores
- Clock and Signal Requirements for Arria V, Cyclone V, and Stratix V Variations
- Clock and Signal Requirements for Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX Variations
- Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP Core Instances
- Sourcing Multiple Tcl Scripts for non-Arria 10 Variations
- 3. Parameter Settings
- 4. Functional Description
- Interfaces
- Clocking and Reset Structure
- Physical Layer
- Transport Layer
- Logical Layer Modules
- Concentrator Register Module
- Maintenance Module
- Input/Output Logical Layer Modules
- Input/Output Avalon-MM Master Module
- RapidIO Packet Data wdptr and Data Size Encoding in Avalon-MM Transactions
- Input/Output Avalon-MM Master Module Timing Diagrams
- Input/Output Avalon-MM Slave Module
- Avalon-MM Burstcount and Byteenable Encoding in RapidIO Packets
- Input/Output Avalon-MM Slave Module Timing Diagrams
- Doorbell Module
- Avalon-ST Pass-Through Interface
- Error Detection and Management
- 5. Signals
- 6. Software Interface
- Physical Layer Registers
- Transport and Logical Layer Registers
- Capability Registers (CARs)
- Command and Status Registers (CSRs)
- Maintenance Interrupt Control Registers
- Receive Maintenance Registers
- Transmit Maintenance Registers
- Transmit Port-Write Registers
- Receive Port-Write Registers
- Input/Output Master Address Mapping Registers
- Input/Output Slave Mapping Registers
- Input/Output Slave Interrupts
- Transport Layer Feature Register
- Error Management Registers
- Doorbell Message Registers
- 7. Testbenches
- Reset, Initialization, and Configuration
- Maintenance Write and Read Transactions
- SWRITE Transactions
- NWRITE_R Transactions
- NWRITE Transactions
- NREAD Transactions
- Doorbell Transactions
- Doorbell and Write Transactions With Transaction Order Preservation
- Port-Write Transactions
- Transactions Across the Avalon-ST Pass-Through Interface
- 8. Qsys Design Example
- A. Initialization Sequence
- C. Porting a RapidIO Design from the Previous Version of the Software
- Additional Information