Altera Temperature Sensor - Manual

Altera Temperature Sensor IP Core User Guide
2015.05.04
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The Altera Temperature Sensor IP core configures the temperature sensing diode (TSD) block to utilize
the temperature measurement feature in the FPGA.
Note: Beginning from the Quartus II software version 14.0, the name of this IP core has been changed
from ALTTEMP_SENSE to Altera Temperature Sensor IP core.
Related Information
Introduction to Altera IP Cores
Provides general information about Altera IP cores.
Altera Temperature Sensor Features
The following table lists the Altera Temperature Sensor IP core features.
Table 1: Altera Temperature Sensor Features
Device Features
Stratix ® V, Stratix IV, Arria ® V, and Arria
V GZ
• An internal TSD with built-in 8-bit analog-to-digital
converter (ADC) circuitry to monitor die temperature
• A clock divider to reduce the frequency of the clock signal
to 1 MHz or less before clocking the ADC
• An asynchronous clear signal to reset the TSD block
Arria 10
• An internal TSD with built-in 10-bit ADC circuitry
clocked by 1 MHz internal oscillator to monitor die
temperature
• Does not require external clock source
• An asynchronous clear signal to reset the TSD block
Note: The Altera Temperature Sensor IP core does not have simulation model files and cannot be
simulated.
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