Instruction Manuals and User Guides 25CPC710 IBM

We have 1 Instruction Manual and User Guide for 25CPC710 IBM

  • IBM 25CPC710 (Pages: 8)
    English: +

    Summary of Contents
    • p. 1/8
      Page 1 of 8 Version 1.0 11/08/01 Abstract This Application Note describes the differences between the CPC710-100+ (DD2) and the CPC710 (DD3.x) versions of the PowerPC Dual PCI/Memory Controller companion chip. The purpose of this note is to provide designers
    • p. 2/8
      Page 2 of 8 Version 1.0 11/08/01 Processor Interface: v Voltage Level and Bus Speed Differences Ø The CPC710 DD3.x revision supports 60x bus operation at speeds of up to 133MHz, at an I/O voltage of 2.5V. This interface voltage level is supported on the
    • p. 3/8
      Page 3 of 8 Version 1.0 11/08/01 Memory Interface: v Extended SDRAM Addressing Ø The signal MADDR13 has been added to support the following additional SDRAM organizations: § 13-12-2, 14-9-2, 14-10-2, 14-11-2, 14-12-2 § Register SDRAM0_MCER [26:29] is used
    • p. 4/8
      Page 4 of 8 Version 1.0 11/08/01 v Extended Addressing of PCI Memory Ø System memory addressing range increased from 2GB to 4GB. The standard addressing capability is 2GB; with the size defined by bits 24-31 of PCI local registers PCILx_PSSIZE. The address
    • p. 5/8
      Page 5 of 8 Version 1.0 11/08/01 plane. In most circumstances, however, it is prudent to place a filter circuit on AVDD; refer to the CPC710 DD3.x User’s Manual for more information. Ø The PLL is now set up and controlled by external signals PLL_RANGE [1:0]
    • p. 6/8
      Page 6 of 8 Version 1.0 11/08/01 v I/O Pin Additions: The following I/Os are new on the DD3 revision: INTERFACE SIGNAL NAME IMPACT 60x bus Interface SYS_BG2_, SYS_BG3_, SYS_MCP2, SYS_MCP3, SYS_HRESET2, SYS_HRESET3, SYS_SRESET2, SYS_SRESET3 New for 4-way
    • p. 7/8
      Page 7 of 8 Version 1.0 11/08/01 Performance Enhancements and Improvements: v The CPC710 DD3.x revision has improvements to support PCI Long Burst Write operations and improvements in the deadlock prevention circuits. These enhancements can be selected by
    • p. 8/8
      Page 8 of 8 Version 1.0 11/08/01 (c) Copyright International Business Machines Corporation 2001 All Rights Reserved Printed in the United States of America November 2001 The following are trademarks of International Business Machines Corporation in the United

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