Document Outline

• Arria 10 Avalon-MM Interface for PCIe Solutions User Guide
• Contents
• 1. Datasheet
  • Arria 10 Avalon-MM Interface for PCIe Datasheet
  • Features
  • Release Information
  • Device Family Support
  • Configurations
  • Example Designs
  • Debug Features
  • IP Core Verification
    • Compatibility Testing Environment
  • Performance and Resource Utilization
  • Recommended Speed Grades
  • Steps in Creating a Design for PCI Express
• 2. Getting Started with the Avalon‑MM Arria 10 Hard IP for PCI Express
  • Running Qsys
  • Generating the Example Design
  • Understanding Simulation Log File Generation
  • Running a Gate-Level Simulation
  • Simulating the Single DWord Design
  • Generating Quartus II Synthesis Files
  • Creating a Quartus II Project
  • Adding Virtual Pin Assignment to the Quartus II Settings File (.qsf)
  • Compiling the Design
  • Programming a Device
  • Understanding Channel Placement Guidelines
• 3. Parameter Settings
  • Arria 10 Avalon-MM System Settings
  • Interface System Settings
  • Base Address Register (BAR) Settings
  • Device Identification Registers
  • PCI Express and PCI Capabilities Parameters
    • Device Capabilities
    • Error Reporting
    • Link Capabilities
    • MSI and MSI-X Capabilities
    • Slot Capabilities
    • Power Management
• 4. Physical Layout of Hard IP In Arria 10 Devices
  • Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates
  • Channel Placement and fPLL Usage for the Gen1 and Gen2 Data Rates
  • Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate
• 5. 64- or 128-Bit Avalon-MM Interface to the Application Layer
  • 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals
  • RX Avalon-MM Master Signals
  • 64- or 128-Bit Bursting TX Avalon-MM Slave Signals
  • Clock Signals
  • Reset
  • Interrupts for Endpoints when Multiple MSI/MSI‑X Support Is Enabled
  • Hard IP Reconfiguration Interface
  • Physical Layer Interface Signals
    • Serial Data Signals
    • PIPE Interface Signals
    • Test Signals
• 6. Registers
  • Correspondence between Configuration Space Registers and the PCIe Specification
  • Type 0 Configuration Space Registers
  • Type 1 Configuration Space Registers
  • PCI Express Capability Structures
  • Altera-Defined VSEC Registers
  • CvP Registers
  • 64- or 128-Bit Avalon-MM Bridge Register Descriptions
    • Avalon-MM to PCI Express Interrupt Registers
      • Avalon-MM to PCI Express Interrupt Status Registers
      • Avalon-MM to PCI Express Interrupt Enable Registers
      • PCI Express Mailbox Registers
      • Avalon-MM-to-PCI Express Address Translation Table
      • PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
      • Avalon-MM Mailbox Registers
      • Control Register Access (CRA) Avalon-MM Slave Port
  • Programming Model for Avalon-MM Root Port
    • Sending a Write TLP
    • Sending a Read TLP or Receiving a Non-Posted Completion TLP
    • PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
    • Root Port TLP Data Registers
  • Uncorrectable Internal Error Mask Register
  • Uncorrectable Internal Error Status Register
  • Correctable Internal Error Mask Register
  • Correctable Internal Error Status Register
• 7. Arria 10 Reset and Clocks
  • Reset Sequence for Hard IP for PCI Express IP Core and Application Layer
  • Clocks
    • Clock Domains
      • coreclkout_hip
      • pld_clk
    • Clock Summary
• 8. Interrupts for Endpoints
  • Enabling MSI or Legacy Interrupts
  • Generation of Avalon-MM Interrupts
  • Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
• 9. Error Handling
  • Physical Layer Errors
  • Data Link Layer Errors
  • Transaction Layer Errors
  • Error Reporting and Data Poisoning
  • Uncorrectable and Correctable Error Status Bits
• 10. IP Core Architecture
  • Top-Level Interfaces
  • Avalon-MM Interface
  • Clocks and Reset
  • Interrupts
  • PIPE
  • Data Link Layer
  • Physical Layer
  • 32-Bit PCI Express Avalon-MM Bridge
    • Avalon‑MM Bridge TLPs
    • Avalon-MM-to-PCI Express Write Requests
    • Avalon-MM-to-PCI Express Upstream Read Requests
    • PCI Express-to-Avalon-MM Read Completions
    • PCI Express-to-Avalon-MM Downstream Write Requests
    • PCI Express-to-Avalon-MM Downstream Read Requests
    • Avalon-MM-to-PCI Express Read Completions
    • PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge
    • Minimizing BAR Sizes and the PCIe Address Space
    • Avalon-MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
  • Completer Only Single Dword Endpoint
    • RX Block
    • Avalon-MM RX Master Block
    • TX Block
    • Interrupt Handler Block
• 11. Design Implementation
  • Making Pin Assignments to Assign I/O Standard to Serial Data Pins
  • Recommended Reset Sequence to Avoid Link Training Issues
  • SDC Timing Constraints
• 12. Throughput Optimization
  • Throughput of Posted Writes
  • Throughput of Non-Posted Reads
• 13. Optional Features
  • Configuration via Protocol (CvP)
  • ECRC
    • ECRC on the RX Path
    • ECRC on the TX Path
• 14. Avalon-MM Testbench and Design Example
  • Arria 10 Avalon-MM Endpoint Testbench
  • Arria 10 Avalon-MM Root Port Testbench
  • Endpoint Design Example
    • BAR/Address Map
  • Avalon-MM Test Driver Module
  • DMA Write Cycles
  • DMA Read Cycles
  • Avalon-MM Root Port Design Example
  • Root Port BFM
    • BFM Memory Map
    • Configuration Space Bus and Device Numbering
    • Configuration of Root Port and Endpoint
    • Issuing Read and Write Transactions to the Application Layer
  • BFM Procedures and Functions
    • ebfm_barwr Procedure
    • ebfm_barwr_imm Procedure
    • ebfm_barrd_wait Procedure
    • ebfm_barrd_nowt Procedure
    • ebfm_cfgwr_imm_wait Procedure
    • ebfm_cfgwr_imm_nowt Procedure
    • ebfm_cfgrd_wait Procedure
    • ebfm_cfgrd_nowt Procedure
    • BFM Configuration Procedures
      • ebfm_cfg_rp_ep Procedure
      • ebfm_cfg_decode_bar Procedure
    • BFM Shared Memory Access Procedures
      • Shared Memory Constants
      • shmem_write
      • shmem_read Function
      • shmem_display Verilog HDL Function
      • shmem_fill Procedure
      • shmem_chk_ok Function
    • BFM Log and Message Procedures
      • ebfm_display Verilog HDL Function
      • ebfm_log_stop_sim Verilog HDL Function
      • ebfm_log_set_suppressed_msg_mask #Verilog HDL Function
      • ebfm_log_set_stop_on_msg_mask Verilog HDL Function
      • ebfm_log_open Verilog HDL Function
      • ebfm_log_close Verilog HDL Function
    • Verilog HDL Formatting Functions
      • himage1
      • himage2
      • himage4
      • himage8
      • himage16
      • dimage1
      • dimage2
      • dimage3
      • dimage4
      • dimage5
      • dimage6
      • dimage7
    • Procedures and Functions Specific to the Chaining DMA Design Example
      • chained_dma_test Procedure
      • dma_rd_test Procedure
      • dma_wr_test Procedure
      • dma_set_rd_desc_data Procedure
      • dma_set_wr_desc_data Procedure
      • dma_set_header Procedure
      • rc_mempoll Procedure
      • msi_poll Procedure
      • dma_set_msi Procedure
      • find_mem_bar Procedure
      • dma_set_rclast Procedure
      • ebfm_display_verb Procedure
  • Setting Up Simulation
    • Changing Between Serial and PIPE Simulation
    • Using the PIPE Interface for Gen1 and Gen2 Variants
    • Viewing the Important PIPE Interface Signals
    • Disabling the Scrambler for Gen1 and Gen2 Simulations
    • Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
• 15. Debugging
  • Simulation Fails To Progress Beyond Polling.Active State
  • Hardware Bring-Up Issues
  • Link Training
  • Use Third-Party PCIe Analyzer
  • BIOS Enumeration Issues
• A. Frequently Asked Questions
• B. Lane Initialization and Reversal
• C. Additional Information
  • Revision History for the Avalon-MM Interface
  • How to Contact Altera
  • Typographic Conventions