Document Outline

• Arria 10 Avalon-ST Interface for PCIe Solutions User Guide
• Contents
• 1. Datasheet
  • Arria 10 Avalon-ST Interface for PCIe Datasheet
    • Arria 10 Features
  • Release Information
  • Device Family Support
  • Configurations
  • Arria 10 Avalon-ST Example Designs
  • Debug Features
  • IP Core Verification
    • Compatibility Testing Environment
  • Performance and Resource Utilization
  • Recommended Speed Grades
  • Steps in Creating a Design for PCI Express
• 2. Getting Started with the Arria 10 Hard IP for PCI Express
  • Qsys Design Flow
    • Generating the Testbench
    • Simulating the Example Design
    • Generating Quartus II Synthesis Files
    • Understanding the Files Generated
    • Understanding Simulation Log File Generation
    • Understanding Physical Placement of the PCIe IP Core
    • Adding Virtual Pin Assignment to the Quartus II Settings File (.qsf)
    • Compiling the Design in the Qsys Design Flow
    • Modifying the Example Design
    • Using the IP Catalog To Generate Your Arria 10 Hard IP for PCI Express as a Separate Component
    • Files Generated for Altera IP Cores
• 3. Getting Started with the Configuration Space Bypass Mode Qsys Example Design
  • Copying the Configuration Space Bypass Mode Example Design
  • Generating the Qsys System
    • Generating Quartus II Synthesis Files
    • Understanding the Generated Files
    • Understanding Simulation Log File Generation
  • Simulating the Example Design
    • Timing for Configuration Read to Function 0 for the 256-Bit Avalon-ST Interface
    • Timing for Configuration Write to Function 0 for the 256-Bit Avalon-ST Interface
    • Timing for Memory Write and Read of Function 1 256-Bit Avalon-ST Interface
    • Partial Transcript for Configuration Space Bypass Simulation
• 4. Parameter Settings
  • System Settings
  • Base Address Register (BAR) and Expansion ROM Settings
  • Base and Limit Registers for Root Ports
  • Device Identification Registers
  • PCI Express and PCI Capabilities Parameters
    • Device Capabilities
    • Error Reporting
    • Link Capabilities
    • MSI and MSI-X Capabilities
    • Slot Capabilities
    • Power Management
  • Vendor Specific Extended Capability (VSEC)
  • PHY Characteristics
• 5. Physical Layout of Hard IP In Arria 10 Devices
  • Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates
  • Channel Placement and fPLL Usage for the Gen1 and Gen2 Data Rates
  • Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate
• 6. Interfaces and Signal Descriptions
  • Avalon‑ST RX Interface
    • Avalon‑ST RX Component Specific Signals
    • Data Alignment and Timing for the 64‑Bit Avalon‑ST RX Interface
    • Data Alignment and Timing for the 128‑Bit Avalon‑ST RX Interface
    • Data Alignment and Timing for 256‑Bit Avalon‑ST RX Interface
    • Tradeoffs to Consider when Enabling Multiple Packets per Cycle
  • Avalon-ST TX Interface
    • Avalon-ST Packets to PCI Express TLPs
    • Data Alignment and Timing for the 64‑Bit Avalon-ST TX Interface
    • Data Alignment and Timing for the 128‑Bit Avalon‑ST TX Interface
    • Data Alignment and Timing for the 256‑Bit Avalon‑ST TX Interface
      • Single Packet Per Cycle
      • Multiple Packets per Cycle on the Avalon-ST TX 256-Bit Interface
    • Root Port Mode Configuration Requests
  • Clock Signals
  • Reset, Status, and Link Training Signals
  • ECRC Forwarding
  • Error Signals
  • Interrupts for Endpoints
  • Interrupts for Root Ports
  • Completion Side Band Signals
  • Parity Signals
  • LMI Signals
  • Transaction Layer Configuration Space Signals
    • Configuration Space Register Access Timing
    • Configuration Space Register Access
  • Hard IP Reconfiguration Interface
  • Power Management Signals
  • Physical Layer Interface Signals
    • Serial Data Signals
    • PIPE Interface Signals
    • Test Signals
• 7. Registers
  • Correspondence between Configuration Space Registers and the PCIe Specification
  • Type 0 Configuration Space Registers
  • PCI Express Capability Structures
  • Altera-Defined VSEC Registers
  • CvP Registers
  • Uncorrectable Internal Error Mask Register
  • Uncorrectable Internal Error Status Register
  • Correctable Internal Error Mask Register
  • Correctable Internal Error Status Register
• 8. Arria 10 Reset and Clocks
  • Reset Sequence for Hard IP for PCI Express IP Core and Application Layer
  • Clocks
    • Clock Domains
      • coreclkout_hip
      • pld_clk
    • Clock Summary
• 9. Interrupts
  • Interrupts for Endpoints
    • MSI Interrupts
    • MSI-X
    • Implementing MSI-X Interrupts
    • Legacy Interrupts
  • Interrupts for Root Ports
• 10. Error Handling
  • Physical Layer Errors
  • Data Link Layer Errors
  • Transaction Layer Errors
  • Error Reporting and Data Poisoning
  • Uncorrectable and Correctable Error Status Bits
• 11. IP Core Architecture
  • Top-Level Interfaces
    • Avalon-ST Interface
    • Clocks and Reset
    • Local Management Interface (LMI Interface)
    • Hard IP Reconfiguration
    • Interrupts
    • PIPE
  • Transaction Layer
    • Configuration Space
    • Error Checking and Handling in Configuration Space Bypass Mode
    • Protocol Extensions Supported
  • Data Link Layer
  • Physical Layer
• 12. Transaction Layer Protocol (TLP) Details
  • Supported Message Types
    • INTX Messages
    • Power Management Messages
    • Error Signaling Messages
    • Locked Transaction Message
    • Slot Power Limit Message
    • Vendor-Defined Messages
    • Hot Plug Messages
  • Transaction Layer Routing Rules
  • Receive Buffer Reordering
    • Using Relaxed Ordering
• 13. Throughput Optimization
  • Throughput of Posted Writes
  • Throughput of Non-Posted Reads
• 14. Design Implementation
  • Making Pin Assignments to Assign I/O Standard to Serial Data Pins
  • Recommended Reset Sequence to Avoid Link Training Issues
  • SDC Timing Constraints
• 15. Optional Features
  • Configuration via Protocol (CvP)
  • ECRC
    • ECRC on the RX Path
    • ECRC on the TX Path
• 16. Hard IP Reconfiguration
• 17. Testbench and Design Example
  • Endpoint Testbench
  • Root Port Testbench
  • Chaining DMA Design Examples
    • BAR/Address Map
    • Chaining DMA Control and Status Registers
    • Chaining DMA Descriptor Tables
  • Test Driver Module
  • DMA Write Cycles
  • DMA Read Cycles
  • Root Port Design Example
  • Root Port BFM
    • BFM Memory Map
    • Configuration Space Bus and Device Numbering
    • Configuration of Root Port and Endpoint
    • Issuing Read and Write Transactions to the Application Layer
  • BFM Procedures and Functions
    • ebfm_barwr Procedure
    • ebfm_barwr_imm Procedure
    • ebfm_barrd_wait Procedure
    • ebfm_barrd_nowt Procedure
    • ebfm_cfgwr_imm_wait Procedure
    • ebfm_cfgwr_imm_nowt Procedure
    • ebfm_cfgrd_wait Procedure
    • ebfm_cfgrd_nowt Procedure
    • BFM Configuration Procedures
      • ebfm_cfg_rp_ep Procedure
      • ebfm_cfg_decode_bar Procedure
    • BFM Shared Memory Access Procedures
      • Shared Memory Constants
      • shmem_write
      • shmem_read Function
      • shmem_display Verilog HDL Function
      • shmem_fill Procedure
      • shmem_chk_ok Function
    • BFM Log and Message Procedures
      • ebfm_display Verilog HDL Function
      • ebfm_log_stop_sim Verilog HDL Function
      • ebfm_log_set_suppressed_msg_mask #Verilog HDL Function
      • ebfm_log_set_stop_on_msg_mask Verilog HDL Function
      • ebfm_log_open Verilog HDL Function
      • ebfm_log_close Verilog HDL Function
    • Verilog HDL Formatting Functions
      • himage1
      • himage2
      • himage4
      • himage8
      • himage16
      • dimage1
      • dimage2
      • dimage3
      • dimage4
      • dimage5
      • dimage6
      • dimage7
    • Procedures and Functions Specific to the Chaining DMA Design Example
      • chained_dma_test Procedure
      • dma_rd_test Procedure
      • dma_wr_test Procedure
      • dma_set_rd_desc_data Procedure
      • dma_set_wr_desc_data Procedure
      • dma_set_header Procedure
      • rc_mempoll Procedure
      • msi_poll Procedure
      • dma_set_msi Procedure
      • find_mem_bar Procedure
      • dma_set_rclast Procedure
      • ebfm_display_verb Procedure
  • Setting Up Simulation
    • Changing Between Serial and PIPE Simulation
    • Using the PIPE Interface for Gen1 and Gen2 Variants
    • Viewing the Important PIPE Interface Signals
    • Disabling the Scrambler for Gen1 and Gen2 Simulations
    • Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
• 18. Debugging
  • Simulation Fails To Progress Beyond Polling.Active State
  • Hardware Bring-Up Issues
  • Link Training
    • Debugging Link Failure in L0 Due To Deassertion of tx_st_ready
  • Use Third-Party PCIe Analyzer
  • BIOS Enumeration Issues
• A. Frequently Asked Questions
• B. Lane Initialization and Reversal
• C. Additional Information
  • Revision History for the Avalon-ST Interface
  • How to Contact Altera
  • Typographic Conventions