Document Outline

• Stratix V Avalon-MM Interface for PCIe Solutions User Guide
• 1. Datasheet
  • Stratix V Avalon-MM Interface for PCIe Datasheet
  • Features
  • Release Information
  • Device Family Support
  • Configurations
  • Example Designs
  • Debug Features
  • IP Core Verification
    • Compatibility Testing Environment
  • Performance and Resource Utilization
  • Recommended Speed Grades
  • Steps in Creating a Design for PCI Express
• 2. Getting Started with the Avalon‑MM Stratix V Hard IP for PCI Express
  • Running Qsys
  • Generating the Example Design
  • Understanding Simulation Log File Generation
  • Running A Gate-Level Simulation
  • Simulating the Single DWord Design
  • Generating Quartus II Synthesis Files
  • Creating a Quartus II Project
  • Compiling the Design
  • Programming a Device
  • Understanding Channel Placement Guidelines
• 3. Parameter Settings
  • Stratix V and Arria V GZ Avalon-MM System Settings
  • Base Address Register (BAR) Settings
  • Device Identification Registers
  • PCI Express and PCI Capabilities Parameters
    • Device Capabilities
    • Error Reporting
    • Link Capabilities
    • MSI and MSI-X Capabilities
    • Power Management
  • Avalon Memory‑Mapped System Settings
• 4. 64- or 128-Bit Avalon-MM Interface to the Application Layer
  • 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals
  • RX Avalon-MM Master Signals
  • 64- or 128-Bit Bursting TX Avalon-MM Slave Signals
  • Clock Signals
  • Reset
  • Interrupts for Endpoints when Multiple MSI/MSI‑X Support Is Enabled
  • Physical Layer Interface Signals
    • Transceiver Reconfiguration
    • Hard IP Status Extension
      • Configuration Space Register Access
      • Configuration Space Register Access Timing
    • Serial Data Signals
      • Physical Layout of Hard IP in Stratix V GX/GT/GS Devices
      • Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
    • PIPE Interface Signals
    • Test Signals
• 5. Registers
  • Correspondence between Configuration Space Registers and the PCIe Specification
  • Type 0 Configuration Space Registers
  • Type 1 Configuration Space Registers
  • PCI Express Capability Structures
  • Altera-Defined VSEC Registers
  • CvP Registers
  • 64- or 128-Bit Avalon-MM Bridge Register Descriptions
    • Avalon-MM to PCI Express Interrupt Registers
      • Avalon-MM to PCI Express Interrupt Status Registers
      • Avalon-MM to PCI Express Interrupt Enable Registers
      • PCI Express Mailbox Registers
      • Avalon-MM-to-PCI Express Address Translation Table
      • PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
      • Avalon-MM Mailbox Registers
      • Control Register Access (CRA) Avalon-MM Slave Port
  • Programming Model for Avalon‑MM Root Port
    • Sending a Write TLP
    • Sending a Read TLP or Receiving a Non-Posted Completion TLP
    • PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
    • Root Port TLP Data Registers
  • Uncorrectable Internal Error Mask Register
  • Uncorrectable Internal Error Status Register
  • Correctable Internal Error Mask Register
  • Correctable Internal Error Status Register
• 6. Reset and Clocks
  • Reset Sequence for Hard IP for PCI Express IP Core and Application Layer
  • Clocks
    • Clock Domains
      • pclk
      • coreclkout_hip
      • pld_clk
    • Clock Summary
• 7. Interrupts for Endpoints
  • Enabling MSI or Legacy Interrupts
  • Generation of Avalon-MM Interrupts
  • Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI‑X Support
• 8. Error Handling
  • Physical Layer Errors
  • Data Link Layer Errors
  • Transaction Layer Errors
  • Error Reporting and Data Poisoning
  • Uncorrectable and Correctable Error Status Bits
• 9. IP Core Architecture
  • Top-Level Interfaces
  • Avalon-MM Interface
  • Clocks and Reset
  • Transceiver Reconfiguration
  • Interrupts
  • PIPE
  • Data Link Layer
  • Physical Layer
  • 32-Bit PCI Express Avalon-MM Bridge
    • Avalon‑MM Bridge TLPs
    • Avalon-MM-to-PCI Express Write Requests
    • Avalon-MM-to-PCI Express Upstream Read Requests
    • PCI Express-to-Avalon-MM Read Completions
    • PCI Express-to-Avalon-MM Downstream Write Requests
    • PCI Express-to-Avalon-MM Downstream Read Requests
    • Avalon-MM-to-PCI Express Read Completions
    • PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge
    • Minimizing BAR Sizes and the PCIe Address Space
    • Avalon-MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
  • Completer Only Single Dword Endpoint
    • RX Block
    • Avalon-MM RX Master Block
    • TX Block
    • Interrupt Handler Block
• 10. Transceiver PHY IP Reconfiguration
  • Connecting the Transceiver Reconfiguration Controller IP Core
  • Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
• 11. Throughput Optimization
  • Throughput of Posted Writes
  • Throughput of Non-Posted Reads
• 12. Design Implementation
  • Making Analog QSF Assignments Using the Assignment Editor
  • Recommended Reset Sequence to Avoid Link Training Issues
  • SDC Timing Constraints
• 13. Optional Features
  • Configuration via Protocol (CvP)
  • ECRC
    • ECRC on the RX Path
    • ECRC on the TX Path
• 14. Debugging
  • Hardware Bring-Up Issues
  • Link Training
    • Debugging Link that Fails To Reach L0
  • Setting Up Simulation
    • Changing Between Serial and PIPE Simulation
    • Using the PIPE Interface for Gen1 and Gen2 Variants
    • Reducing Counter Values for Serial Simulations
    • Disable the Scrambler for Gen1 and Gen2 Simulations
    • Changing between the Hard and Soft Reset Controller
  • Use Third-Party PCIe Analyzer
  • BIOS Enumeration Issues
• A. Transaction Layer Packet (TLP) Header Formats
  • TLP Packet Formats with Data Payload
• B. Lane Initialization and Reversal
• C. Additional Information
  • Revision History for the Avalon-MM Interface
  • How to Contact Altera
  • Typographic Conventions