Document Outline

• 13.1CPRI MegaCore Function User Guide
  • Contents
  • 1. About This MegaCore Function
    • General Description
    • CPRI IP Core Features
    • Device Family Support
    • MegaCore Verification
    • Performance and Resource Utilization
    • Release Information
    • Installation and Licensing
      • OpenCore Plus Evaluation
      • OpenCore Plus Time-Out Behavior
  • 2. Getting Started
    • MegaWizard Plug-In Manager Design Flow
      • Specifying Parameters
      • Simulation Files
      • Simulating the Design
    • Integrating the CPRI IP Core in a Design
      • Supporting the Transceivers
      • Specifying Constraints
    • Compiling and Programming the Device
    • Instantiating Multiple CPRI IP Cores
  • 3. Parameter Settings
    • Physical Layer Parameters
      • Operation Mode Parameter
      • Line Rate Parameter
      • Enable Autorate Negotiation
      • Transceiver Starting Channel Number
      • Rx Elastic Buffer Depth
      • Transceiver Reference Clock Frequency
      • Automatic Round-Trip Delay Calibration
    • Data Link Layer Parameters
      • Include MAC Block
      • Include HDLC Block
    • Application Layer Parameters
      • Mapping Mode
      • Number of Antenna-Carrier Interfaces
      • Enable Internally-Clocked Synchronization Mode
      • Vendor-Specific Space (VSS) Access through CPU Interface
  • 4. Functional Description
    • Architecture Overview
    • Clocking Structure
      • CPRI IP Core Clocks
      • Clock Diagrams for the CPRI IP Core
        • Clock Diagrams for Most CPRI IP Core Variations
        • Clock Diagrams for CPRI IP Core Arria V GT Variations at 9830.4 Mbps
      • Dynamically Switching Clock Mode
      • CPRI Communication Link Line Rates
    • Reset Requirements
    • MAP Interface
      • MAP Interface Mapping Modes
        • Basic AxC Mapping Mode
        • Advanced AxC Mapping Modes
      • MAP Receiver Interface
        • MAP Receiver Interface Signals in Different Synchronization Modes
        • MAP Receiver in FIFO Mode
        • MAP Receiver in Synchronous Buffer Mode
        • MAP Receiver in the Internally-Clocked Mode
      • MAP Transmitter Interface
        • MAP Transmitter Interface Signals in Different Synchronization Modes
        • MAP Transmitter in FIFO Mode
        • MAP Transmitter in Synchronous Buffer Mode
        • MAP Transmitter in the Internally-clocked Mode
    • Auxiliary Interface
      • AUX Receiver Module
      • AUX Transmitter Module
    • Media Independent Interface to an External Ethernet Block
      • MII Transmitter
      • MII Receiver
    • CPU Interface
      • Accessing the Hyperframe Control Words
        • Recording and Retrieving the Incoming Control Words
        • Writing the Outgoing Control Words
        • Control Word Order
        • Control Word Transmission Example
        • Control Word Retrieval Example
      • Accessing the Ethernet Channel
        • Transmitting Ethernet Traffic
        • Receiving Ethernet Traffic
      • Accessing the HDLC Channel
    • CPRI Protocol Interface Layer (Physical Layer)
      • Features
      • Physical Layer Architecture
      • Ensuring the Physical Layer Routes Your Data as Expected
      • Receiver
        • High-Speed Transceiver
        • Rx Elastic Buffer
        • Descrambling
        • Frame Synchronization
        • Alarm Indications
        • Reset Control Word
      • Transmitter
        • Scrambling
        • Tx Elastic Buffer
        • High-Speed Transceiver
  • 5. Testing Features
    • Loopback Modes
      • External Loopback
      • Internal Reverse Loopback
        • Physical Layer Loopback Mode
        • Reverse Loopback Through CPRI Rx and Tx Buffers
    • PRBS Generation and Validation
    • Achieving Link Synchronization Without an REC Master
  • 6. Signals
    • MAP Interface Signals
      • MAP Receiver Signals
      • MAP Transmitter Signals
    • Auxiliary Interface Signals
      • AUX Receiver Signals
      • AUX Transmitter Signals
      • Extended Rx Status Signals
    • CPRI MII Signals
      • CPRI MII Receiver Signals
      • CPRI MII Transmitter Signals
    • CPU Interface Signals
    • Physical Layer Signals
      • CPRI Data Signals
      • Layer 1 Clock and Reset Signals
      • Layer 1 Error Signal
      • Autorate Negotiation Signals
      • Transceiver Signals
    • Clock and Reset Interface Signals
  • 7. Software Interface
    • CPRI Protocol Interface Registers
    • MAP Interface and AUX Interface Configuration Registers
    • Ethernet Registers
    • HDLC Registers
  • 8. CPRI IP Core Demonstration Testbench
    • Test Sequence
    • Reset, Frame Synchronization, and Initialization
    • Running the Testbench
  • A. Initialization Sequence
  • B. Implementing CPRI Link Autorate Negotiation
    • Design Implementation
    • Configuring the CPRI IP Core for Autorate Negotiation
    • Running Autorate Negotiation
    • Autorate Negotiation From 9.8304 Gbps in Arria V GT Variations
  • C. CPRI Autorate Negotiation Testbench
    • Test Sequence
    • Running the Autorate Negotiation Testbench
  • D. Advanced AxC Mapping Modes
    • Backward Compability
    • Advanced Mapping Mode Similarities and Differences
      • Fifteen-Bit Width Mode
      • Sixteen-Bit Width Mode
  • E. Delay Measurement and Calibration
    • Delay Measurement and Calibration Features
    • Delay Requirements
    • Single-Hop Delay Measurement
      • Rx Path Delay
        • Most CPRI IP Core Variations
        • Arria V GT 9.8 Gbps
      • Tx Path Delay
        • Most CPRI IP Core Variations
        • Arria V GT 9.8 Gbps
      • Toffset
      • Round-Trip Delay
      • Round-Trip Cable Delay
      • Tx Bitslip Delay in the Round-Trip Delay Calculation
      • Dynamic Pipelining for Automatic Round-Trip Delay Calibration
      • Round-Trip and Cable Delay Calculation Examples
        • Round-Trip and Cable Delay Calculation Example 1: Two Stratix IV GX Devices
        • Round-Trip and Cable Delay Calculation Example 2: Two Arria II GX Devices
        • Round-Trip and Cable Delay Calculation Example 3: Two Different Device Families
        • Round-Trip and Cable Delay Calculation Example 4: Two Different Device Families
    • Multi-Hop Delay Measurement
      • Round-Trip Delay Calculation
      • Round-Trip Cable Delay Calculation
      • Two-Hop Round-Trip and Cable Delay Calculation Example
  • F. Integrating the CPRI IP Core Timing Constraints in the Full Design
  • G. Porting a CPRI IP Core from the Previous Version of the Software
  • Additional Information
    • Document Revision History
    • How to Contact Altera
    • Typographic Conventions