Document Outline

• Cyclone V GT FPGA Development Kit User Guide
  • Contents
  • 1. About This Kit
    • Kit Features
      • Hardware
      • Software
        • Quartus II Software
        • Cyclone V GT FPGA Development Kit Installer
  • 2. Getting Started
    • Before You Begin
    • Inspecting the Boards
    • References for Getting Started
  • 3. Software Installation
    • Installing the Quartus II Subscription Edition Software
    • Activating Your License
    • Installing the Development Kit
    • Installing the USB-Blaster II Driver
  • 4. Development Board Setup
    • Setting Up the Board
    • Factory Default Switch and Jumper Settings
    • Restoring the MAX V CPLD to the Factory Settings
    • Restoring the Flash Device to the Factory Settings
    • Configuring the FPGA Using the Quartus II Programmer
  • 5. Board Update Portal
    • Connecting to the Board Update Portal Web Page
    • Using the Board Update Portal to Write User Designs
  • 6. Board Test System
    • Preparing to Run the Board Test System
    • Running the Board Test System
    • Using the Board Test System
      • The Configure Menu
      • The System Info Tab
        • Power Monitor
        • Board Information
        • MAX V Registers
        • JTAG Chain
      • The GPIO Tab
        • Character LCD and Display
        • User DIP Switches
        • User LEDs
        • Push Button Switches
      • The Flash Tab
        • Read and Start Address
        • Range
        • Write
        • Random Test
        • CFI Query
        • Increment Test
        • Reset
        • Erase
        • Flash Memory Table and Flash Memory Map
      • The DDR3x40 and DDR3x64 Tabs
        • Start
        • Stop
        • Performance Indicators
        • Error Control
        • Number of Addresses to Write and Read
      • The HSMA Tab
        • Start, Stop
        • XCRV, LVDS, CMOS
      • The HSMB Tab
        • Start, Stop
        • XCRV and CMOS
    • The Power Monitor
      • Power Monitor Features
      • Power Monitor Controls
        • General Information
        • Power Information
        • Power Graph
        • Graph Settings
        • Reset
    • The Clock Control
      • Clock Control Features
      • Clock Control Controls
        • Serial Port Registers
        • fXTAL
        • Target Frequency
        • Clear
        • Set New Frequency
  • A. Programming the Flash Memory Device
    • CFI Flash Memory Map
    • Preparing Design Files for Flash Programming
    • Creating Flash Files Using the Nios II EDS
    • Converting Additional Files
    • Programming Flash Memory Using the Nios II EDS
    • Programming Flash Memory Using the Board Update Portal
  • Additional Information
    • Document Revision History
    • How to Contact Altera
    • Typographic Conventions