Document Outline

• External Memory Interface Handbook Volume 3 Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
  • Contents
  • 1. About This IP
    • Release Information
    • Device Family Support
    • Features
    • Unsupported Features
    • MegaCore Verification
    • Resource Utilization
    • System Requirements
    • Installation and Licensing
      • Free Evaluation
      • OpenCore Plus Time-Out Behavior
  • 2. Getting Started
    • Design Flow
    • SOPC Builder Flow
      • Specifying Parameters
      • Completing the SOPC Builder System
    • Qsys Flow
      • Specifying Parameters
      • Completing the Qsys System
    • MegaWizard Plug-In Manager Flow
      • Specifying Parameters
    • HardCopy Guidelines
    • Generated Files
  • 3. Parameter Settings
    • ALTMEMPHY Parameter Settings
      • Memory Settings
        • Using the Preset Editor to Create a Custom Memory Preset
        • Derating Memory Setup and Hold Timing
      • PHY Settings
      • Board Settings
    • DDR or DDR2 SDRAM Controller with ALTMEMPHY Parameter Settings
      • Controller Settings
  • 4. Compiling and Simulating
    • Compiling the Design
    • Simulating the Design
  • 5. Functional Description—ALTMEMPHY
    • Block Description
      • Calibration
      • Address and Command Datapath
        • Arria GX, Arria II GX, Cyclone III, HardCopy II, Stratix II, and Stratix II GX Devices
        • Stratix III and Stratix IV Devices
      • Clock and Reset Management
        • Arria GX, Arria II GX, HardCopy II, Stratix II, and Stratix II GX Devices
        • Cyclone III Devices
        • Stratix III and Stratix IV Devices
      • Read Datapath
        • Arria GX, Arria II GX, HardCopy II, Stratix II, and Stratix II GX Devices
        • Cyclone III Devices
        • Stratix III and Stratix IV Devices
      • Write Datapath
        • Arria GX, Arria II GX, Cyclone III, HardCopy II, Stratix II, and Stratix II GX Devices
        • Stratix III and Stratix IV Devices
    • ALTMEMPHY Signals
    • PHY-to-Controller Interfaces
    • Using a Custom Controller
      • Preliminary Steps
      • Design Considerations
      • Clocks and Resets
      • Calibration Process Requirements
      • Other Local Interface Requirements
      • Address and Command Interfacing
      • Handshake Mechanism Between Read Commands and Read Data
      • Handshake Mechanism Between Write Commands and Write Data
      • Partial Write Operations
      • Using a Custom Controller with the TimeQuest Timing Analyzer
  • 6. Functional Description— High-Performance Controller II
    • Memory Controller Architecture
      • Avalon-ST Input Interface
      • Command Generator
      • Timing Bank Pool
      • Arbiter
        • Arbitration Rules
      • Rank Timer
      • Read Data Buffer
      • Write Data Buffer
      • ECC Block
      • AFI Interface
      • CSR Interface
    • Controller Features Descriptions
      • Data Reordering
      • Pre-emptive Bank Management
      • Quasi-1T and Quasi-2T
      • User Autoprecharge Commands
      • Address and Command Decoding Logic
      • Low-Power Logic
        • User-Controlled Self-Refresh
        • Automatic Power-Down with Programmable Time-Out
      • ODT Generation Logic
        • DDR2 SDRAM
      • ECC
        • Partial Writes
        • Partial Bursts
    • External Interfaces
      • Clock and Reset Interface
      • Avalon-ST Data Slave Interface
      • Controller-PHY Interface
      • Memory Side-Band Signals
        • Self-Refresh (Low Power) Interface
        • User-Controller Refresh Interface
        • Configuration and Status Register (CSR) Interface
    • Top-Level Signals Description
    • Sequence of Operations
      • Write Command
      • Read Command
      • Read-Modify-Write Command
    • Example Top-Level File
      • Example Driver
    • Register Maps
      • ALTMEMPHY Register Map
      • Controller Register Map
  • 7. Latency
  • 8. Timing Diagrams
    • DDR and DDR2 High-Performance Controllers II
      • Half-Rate Read
      • Half-Rate Write
      • Full-Rate Read
      • Full-Rate Write
  • Additional Information
    • Document Revision History
    • How to Contact Altera
    • Typographic Conventions