Document Outline

• DisplayPort IP Core User Guide
  • Contents
  • 1. DisplayPort IP Core Quick Reference
  • 2. About This IP Core
    • Device Family Support
    • IP Core Verification
    • Performance and Resource Utilization
  • 3. Getting Started
    • Installing and Licensing IP Cores
      • OpenCore Plus IP Evaluation
    • Specifying IP Core Parameters and Options
    • Simulating the Design
      • Simulating with the ModelSim Simulator
    • Compiling the Full Design and Programming the FPGA
  • 4. DisplayPort Source
    • Source Overview
    • Source Functional Description
      • Main Data Path
        • Packetizer Path
        • Measurement Path
        • Blank Generator Path
        • Multiplexer
      • Embedded DisplayPort (eDP) Support
    • Source Parameters
    • Source Interfaces
      • Controller Interface
      • AUX Interface
      • Video Interface
      • TX Transceiver Interface
      • Transceiver Reconfiguration Interface
      • Transceiver Analog Reconfiguration Interface
      • Secondary Stream Interface
      • Audio Interface
      • MSA Interface
    • Source Clock Tree
  • 5. DisplayPort Sink
    • Sink Overview
    • Sink Functional Description
      • Embedded DisplayPort (eDP) Support
    • Sink Parameters
    • Sink Interfaces
      • Controller Interface
      • AUX Interface
        • AUX Debug Interface
        • EDID Interface
      • Debugging Interface
        • Link Parameters Interface
        • Video Stream Out Interface
      • Video Interface
        • Clocked Video Input Interface
      • RX Transceiver Interface
      • Transceiver Reconfiguration Interface
      • Secondary Stream Interface
      • Audio Interface
      • MSA Interface
    • Sink Clock Tree
  • 6. DisplayPort IP Core Hardware Demonstration
    • Clock Recovery Core
      • Clock Recovery Core Parameters
      • Clock Recovery Interface
        • Video Input Port
    • Transceiver and Clocking
    • Required Hardware
    • Design Walkthrough
      • Set Up the Hardware
      • Copy the Design Files to Your Working Directory
      • Build the FPGA Design
      • Load, and Run the Software
      • View the Results
  • 7. DisplayPort IP Core Simulation Example
    • Design Walkthrough
      • Copy the Simulation Files to Your Working Directory
      • Generate the IP Simulation Files and Scripts, and Compile and Simulate
      • View the Results
        • Arria 10 Finite-State Machine (FSM)
  • 8. DisplayPort API Reference
    • Using the Library
    • btc_dprx_syslib API Reference
    • btc_dprx_aux_get_request
    • btc_dprx_aux_handler
    • btc_dprx_aux_post_reply
    • btc_dprx_baseaddr
    • btc_dprx_dpcd_gpu_access
    • btc_dprx_edid_set
    • btc_dprx_hpd_get
    • btc_dprx_hpd_pulse
    • btc_dprx_hpd_set
    • btc_dprx_syslib_add_rx
    • btc_dprx_syslib_info
    • btc_dprx_syslib_init
    • btc_dprx_syslib_monitor
    • btc_dptx_syslib API Reference
    • btc_dptx_aux_i2c_read
    • btc_dptx_aux_i2c_write
    • btc_dptx_aux_read
    • btc_dptx_aux_write
    • btc_dptx_baseaddr
    • btc_dptx_edid_block_read
    • btc_dptx_edid_read
    • btc_dptx_fast_link_training
    • btc_dptx_link_training
    • btc_dptx_set_color_space
    • btc_dptx_syslib_init
    • btc_dptx_syslib_monitor
    • btc_dptx_test_autom
    • btc_dptx_video_enable
    • btc_dpxx_syslib Additional Types
    • btc_dprx_syslib Supported DPCD Locations
  • 9. DisplayPort Source Register Map and DPCD Locations
    • Source General Registers
      • DPTX_TX_CONTROL
      • DPTX_TX_STATUS
    • Source MSA Registers
      • DPTX0_MSA_MVID
      • DPTX0_MSA_NVID
      • DPTX0_MSA_HTOTAL
      • DPTX0_MSA_VTOTAL
      • DPTX0_MSA_HSP
      • DPTX0_MSA_HSW
      • DPTX0_MSA_HSTART
      • DPTX0_MSA_VSTART
      • DPTX0_MSA_VSP
      • DPTX0_MSA_VSW
      • DPTX0_MSA_HWIDTH
      • DPTX0_MSA_VHEIGHT
      • DPTX0_MSA_MISC0
      • DPTX0_MSA_MISC1
      • DPTX0_MSA_COLOUR
    • Source Link Voltage and Pre-Emphasis Controls
      • DPTX_PRE_VOLT0
      • DPTX_PRE_VOLT1
      • DPTX_PRE_VOLT2
      • DPTX_PRE_VOLT3
      • DPTX_RECONFIG
    • Source Timestamp
    • Source Audio Registers
    • Source CRC Registers
    • Source MST Registers
      • DPTX_MST_VCPTAB0
      • DPTX_MST_VCPTAB1
      • DPTX_MST_VCPTAB2
      • DPTX_MST_VCPTAB3
      • DPTX_MST_VCPTAB4
      • DPTX_MST_VCPTAB5
      • DPTX_MST_VCPTAB6
      • DPTX_MST_VCPTAB7
      • DPTX_MST_TAVG_TS
    • Source AUX Controller Interface
      • DPTX_AUX_CONTROL
      • DPTX_AUX_CMD
      • DPTX_AUX_BYTE0
      • DPTX_AUX_BYTE1
      • DPTX_AUX_BYTE2
      • DPTX_AUX_BYTE3
      • DPTX_AUX_BYTE4
      • DPTX_AUX_BYTE5
      • DPTX_AUX_BYTE6
      • DPTX_AUX_BYTE7
      • DPTX_AUX_BYTE8
      • DPTX_AUX_BYTE9
      • DPTX_AUX_BYTE10
      • DPTX_AUX_BYTE11
      • DPTX_AUX_BYTE12
      • DPTX_AUX_BYTE13
      • DPTX_AUX_BYTE14
      • DPTX_AUX_BYTE15
      • DPTX_AUX_BYTE16
      • DPTX_AUX_BYTE17
      • DPTX_AUX_BYTE18
      • DPTX_AUX_RESET
    • Source-Supported DPCD Locations
  • 10. DisplayPort Sink Register Map and DPCD Locations
    • Sink General Registers
      • DPRX_RX_CONTROL
      • DPRX_RX_STATUS
      • DPRX_BER_CONTROL
      • DPRX_BER_CNT0
      • DPRX_BER_CNT1
    • Sink Timestamp
    • Sink Bit-Error Counters
      • DPRX_BER_CNTI0
      • DPRX_BER_CNTI1
    • Sink MSA Registers
      • DPRX0_MSA_MVID
      • DPRX0_MSA_NVID
      • DPRX0_MSA_HTOTAL
      • DPRX0_MSA_VTOTAL
      • DPRX0_MSA_HSP
      • DPRX0_MSA_HSW
      • DPRX0_MSA_HSTART
      • DPRX0_MSA_VSTART
      • DPRX0_MSA_VSP
      • DPRX0_MSA_VSW
      • DPRX0_MSA_HWIDTH
      • DPRX0_MSA_VHEIGHT
      • DPRX0_MSA_MISC0
      • DPRX0_MSA_MISC1
      • DPRX0_VBID
    • Sink Audio Registers
      • DPRX0_AUD_MAUD
      • DPRX0_AUD_NAUD
      • DPRX0_AUD_AIF0
      • DPRX0_AUD_AIF1
      • DPRX0_AUD_AIF2
      • DPRX0_AUD_AIF3
      • DPRX0_AUD_AIF4
    • Sink MST Registers
      • DPRX_MST_VCPTAB0
      • DPRX_MST_VCPTAB1
      • DPRX_MST_VCPTAB2
      • DPRX_MST_VCPTAB3
      • DPRX_MST_VCPTAB4
      • DPRX_MST_VCPTAB5
      • DPRX_MST_VCPTAB6
      • DPRX_MST_VCPTAB7
    • Sink AUX Controller Interface
      • DPRX_AUX_CONTROL
      • DPRX_AUX_STATUS
      • DPRX_AUX_COMMAND
      • DPRX_AUX_BYTE0
      • DPRX_AUX_BYTE1
      • DPRX_AUX_BYTE2
      • DPRX_AUX_BYTE3
      • DPRX_AUX_BYTE4
      • DPRX_AUX_BYTE5
      • DPRX_AUX_BYTE6
      • DPRX_AUX_BYTE7
      • DPRX_AUX_BYTE8
      • DPRX_AUX_BYTE9
      • DPRX_AUX_BYTE10
      • DPRX_AUX_BYTE11
      • DPRX_AUX_BYTE12
      • DPRX_AUX_BYTE13
      • DPRX_AUX_BYTE14
      • DPRX_AUX_BYTE15
      • DPRX_AUX_BYTE16
      • DPRX_AUX_BYTE17
      • DPRX_AUX_BYTE18
      • DPRX_AUX_I2C0
      • DPRX_AUX_I2C1
      • DPRX_AUX_RESET
      • DPRX_AUX_HPD
    • Sink-Supported DPCD Locations
  • A. Additional Information
    • Document Revision History