Document Outline

• Integer Arithmetic IP Cores User Guide
• Contents
• 1. Integer Arithmetic Megafunctions
  • Design Example Files
  • Installing and Licensing IP Cores
  • Customizing and Generating IP Cores
  • IP Catalog and Parameter Editor
  • Using the Parameter Editor
  • Specifying IP Core Parameters and Options
  • Specifying IP Core Parameters and Options (Legacy Parameter Editors)
    • Files Generated for Altera IP Cores (Legacy Parameter Editor)
  • Upgrading IP Cores
  • Migrating IP Cores to a Different Device
  • Simulating Altera IP Cores in other EDA Tools
• 2. LPM_COUNTER (Counter)
  • Features
  • Resource Utilization and Performance
  • Verilog HDL Prototype
  • VHDL Component Declaration
  • VHDL LIBRARY_USE Declaration
  • Ports
  • Parameters
• 3. LPM_DIVIDE (Divider)
  • Features
  • Resource Utilization and Performance
  • Verilog HDL Prototype
  • VHDL Component Declaration
  • VHDL LIBRARY_USE Declaration
  • Ports
  • Parameters
• 4. LPM_MULT (Multiplier)
  • Features
  • Resource Utilization and Performance
  • Verilog HDL Prototype
  • VHDL Component Declaration
  • VHDL LIBRARY_USE Declaration
  • LPM_MULT Ports
  • LPM_MULT Parameters
• 5. ALTECC (Error Correction Code: Encoder/Decoder)
  • ALTECC_ENCODER Features
  • Resource Utilization and Performance
  • Verilog HDL Prototype (ALTECC_ENCODER)
  • Verilog HDL Prototype (ALTECC_DECODER)
  • VHDL Component Declaration (ALTECC_ENCODER)
  • VHDL Component Declaration (ALTECC_DECODER)
  • VHDL LIBRARY_USE Declaration
  • Ports (ALTECC_ENCODER)
  • Ports (ALTECC_DECODER)
  • Parameters (ALTECC_ENCODER)
  • Parameters (ALTECC_DECODER)
  • Design Example 1: ALTECC_ENCODER
    • Understanding the Simulation Results
      • Design Example 1: Calculation of Parity Bits
  • Design Example 2: ALTECC_DECODER
    • Understanding the Simulation Results
• 6. ALTERA_MULT_ADD (Multiply-Adder)
  • Features
    • Pre-adder
      • Pre-adder Simple Mode
      • Pre-adder Coefficient Mode
      • Pre-adder Input Mode
      • Pre-adder Square Mode
      • Pre-adder Constant Mode
    • Systolic Delay Register
    • Pre-load Constant
    • Double Accumulator
  • Verilog HDL Prototype
  • VHDL Component Declaration
  • VHDL LIBRARY_USE Declaration
  • Ports
  • ALTERA_MULT_ADD Parameters
  • Design Example: Implementing a Simple Finite Impulse Response (FIR) Filter
  • Understanding the Simulation Results
• 7. ALTMEMMULT (Memory-based Constant Coefficient Multiplier)
  • Features
  • Resource Utilization and Performance
  • Verilog HDL Prototype
  • VHDL Component Declaration
  • Ports
  • Parameters
  • Design Example: 8 × 8 Multiplier
  • Understanding the Simulation Results
• 8. ALTMULT_ACCUM (Multiply-Accumulate)
  • Features
  • Resource Utilization and Performance
  • Verilog HDL Prototype
  • VHDL Component Declaration
  • VHDL LIBRARY_USE Declaration
  • ALTMULT_ACCUM Ports
  • ALTMULT_ACCUM Parameters
  • Design Example: Shift Accumulator
  • Understanding the Simulation Results
• 9. ALTMULT_ADD (Multiply-Adder)
  • Features
    • Pre-adder
      • Pre-adder Simple Mode
      • Pre-adder Coefficient Mode
      • Pre-adder Input Mode
      • Pre-adder Square Mode
      • Pre-adder Constant Mode
    • Systolic Delay Register
    • Pre-load Constant
    • Double Accumulator
  • Resource Utilization and Performance
  • Verilog HDL Prototype
  • VHDL Component Declaration
  • VHDL LIBRARY_USE Declaration
  • ALTMULT_ADD Ports
  • ALTMULT_ADD Parameters
  • Design Example: Implementing a Simple Finite Impulse Response (FIR) Filter
  • Understanding the Simulation Results
• 10. ALTMULT_COMPLEX (Complex Multiplier)
  • Complex Multiplication
  • Canonical Representation
  • Conventional Representation
  • Features
  • Resource Utilization and Performance
  • Verilog HDL Prototype
  • VHDL Component Declaration
  • VHDL LIBRARY_USE Declaration
  • ALTMULT_COMPLEX Ports
  • ALTMULT_COMPLEX Parameters
  • Design Example: Multiplication of 8-bit Complex Numbers Using Canonical Representation
  • Understanding the Simulation Results
• 11. ALTSQRT (Integer Square Root)
  • Features
  • Resource Utilization and Performance
  • Verilog HDL Prototype
  • VHDL Component Declaration
  • VHDL LIBRARY_USE Declaration
  • Ports
  • Parameters
  • Design Example: 9-bit Square Root
  • Understanding the Simulation Results
• 12. PARALLEL_ADD (Parallel Adder)
  • Feature
  • Resource Utilization and Performance
  • Verilog HDL Prototype
  • VHDL Component Declaration
  • VHDL LIBRARY_USE Declaration
  • Ports
  • Parameters
  • Design Example: Shift Accumulator
  • Understanding the Simulation Results
• 13. Document Revision History