Document Outline

• Interlaken MegaCore Function User Guide
  • Contents
  • 1. About This MegaCore Function
    • Features
    • Device Family Support
    • MegaCore Verification
    • Performance and Resource Utilization
    • Release Information
    • Installation and Licensing
      • Interlaken MegaCore Function Licenses
      • OpenCore Evaluation
  • 2. Getting Started
    • Design Flows
      • MegaWizard Plug-In Manager Design Flow Summary
      • Qsys Design Flow Summary
    • MegaWizard Plug-in Manager Design Flow
      • Specifying Parameters and Generating the MegaCore Function
      • Simulating the Interlaken MegaCore Function
      • Instantiating the MegaCore Function in Your Design
    • Qsys Design Flow
      • Specifying Parameters
      • Completing the Qsys System
      • Simulating the System
    • Specifying Constraints
      • Hard PLL Assignment Constraints
      • I/O Standard Constraints
    • Compiling the Full Design and Programming the FPGA
  • 3. Parameter Settings
    • General Parameters
      • Operational Mode
      • Number of Lanes
      • Lane Rate
      • Number of Words in Meta Frame
      • Exclude Transceiver
      • Enable Out-of-Band Flow Control
    • In-Band Flow Control Parameters
      • Expose Calendar Ports
      • Number of Sixteen-Bit Calendar Pages
    • Burst Parameters
      • Enable Dynamic Configuration of BurstMax and BurstShort Parameters
      • Parameterized Static BurstMax Value
      • Parameterized Static BurstShort Value
  • 4. Functional Description
    • Architecture Overview
    • Interfaces Overview
      • Interlaken Interface
      • Application Interface
        • Avalon-ST Interface
        • Optional In-Band Flow Control and Dynamic Configuration Signals
      • Out-of-Band Flow Control Interface
    • Clocking and Reset Structure
      • MegaCore Function MAC Clock Domains
      • Interlaken Interface Clocks
      • Out-of-Band Flow Control Block Clocks
      • Clock Diagrams for the Interlaken MegaCore Function
      • Interlaken MegaCore Function Recommended Clock Rates
        • MAC Clock Verified Frequency
        • PCS Clock Frequencies
        • Transceiver Reference Clock Recommended Frequency and Source
        • Out-of-Band Flow Control Block Recommended Clock Frequencies
      • Reset for Interlaken MegaCore Functions
    • Transmit Path
      • Arbiter
        • Arbiter and Application Behavior
        • Application Data Transfer Example
      • TX MAC
      • TX PCS
    • Receive Path
      • RX PCS
      • RX MAC
      • Channel Filtering Blocks
      • Packet Regrouper
    • Calendar and Status Block
      • Lane Status Block
      • TX Calendar Control Block and In-Band Flow Control Calendar Bits
        • Behavior with Hidden Calendar Ports
        • Behavior with Exposed Calendar Ports
      • Status Counters
    • High-Speed I/O Block
      • FIFO Buffers and Pipeline Registers
      • Transceivers
    • Out-of-Band Flow Control Block
      • RX Out-of-Band Flow Control Block
      • TX Out-of-Band Flow Control Block
      • Out-of-Band Flow Control Block Signals
  • 5. Signals
    • Interlaken Interface and External Transceiver Interface Signals
      • Interlaken Interface Data and Clock Signals
      • Interlaken Interface Status Signals
    • Interlaken MegaCore Function Reset Signals
    • Application Interface Signals
      • RX Application Interface Signals
      • TX Application Interface Signals
    • Out-of-Band Flow Control Interface Signals
      • RX Out-of-Band Flow Control Signals
      • TX Out-of-Band Flow Control Interface Signals
  • 6. Qsys Design Examples
    • Design Examples Overview
    • Interlaken Sample Channel Client Component
    • Design Example Simulation Sequence
    • Running a Design Example
      • Setting Up the Design Example
      • Creating the Quartus II Project and Generating the Qsys System
      • Simulating the System
      • Compiling and Programming the Device
  • A. Initializing the Interlaken MegaCore Function
    • Configuration and Reset
    • Expected Behavior at Initialization
    • Troubleshooting an Interlaken Link
  • B. Excluding Transceivers for Faster Simulation
    • External Transceiver Interface Clocks
    • External Transceiver Interface Data and Clock Signals
    • Reset in Interlaken MegaCore Functions Without Transceivers
      • Reset Signals
      • Required Reset Sequence
  • C. Closing Timing on 10- and 20-lane Designs
  • D. Porting an Interlaken Design from the Previous Version of the Software
  • Additional Information
    • Document Revision History
    • How to Contact Altera
    • Typographic Conventions