Document Outline

• IP Compiler for PCI Express User Guide
  • 1. Datasheet
    • Features
    • Release Information
    • Device Family Support
    • General Description
      • Support for IP Compiler for PCI Express Hard IP
      • External PHY Support
      • Debug Features
    • IP Core Verification
      • Simulation Environment
      • Compatibility Testing Environment
    • Performance and Resource Utilization
    • Recommended Speed Grades
  • 2. Getting Started
    • Installing and Licensing IP Cores
      • OpenCore Plus IP Evaluation
    • IP Catalog and Parameter Editor
      • Using the Parameter Editor
    • Upgrading Outdated IP Cores
      • Upgrading IP Cores at the Command Line
    • Parameterizing the IP Compiler for PCI Express
    • Viewing the Generated Files
    • Simulating the Design
    • Constraining the Design
      • Specifying Device and Pin Assignments
      • Specifying QSF Constraints
    • Compiling the Design
    • Reusing the Example Design
  • 3. Parameter Settings
    • Parameters in the Qsys Design Flow
      • System Settings
      • PCI Base Address Registers
      • Device Identification Registers
      • Link Capabilities
      • Error Reporting
      • Buffer Configuration
      • Avalon-MM Settings
      • Address Translation
      • Address Translation Table Contents
    • IP Core Parameters
      • System Settings
      • PCI Registers
      • Capabilities Parameters
      • Buffer Setup
      • Power Management
      • Avalon-MM Configuration
  • 4. IP Core Architecture
    • Application Interfaces
      • Avalon-ST Application Interface
        • RX Datapath
        • TX Datapath
        • LMI Interface (Hard IP Only)
        • PCI Express Reconfiguration Block Interface (Hard IP Only)
        • MSI (Message Signal Interrupt) Datapath
        • Incremental Compilation
      • Avalon-MM Interface
    • Transaction Layer
      • Transmit Virtual Channel Arbitration
      • Configuration Space
    • Data Link Layer
    • Physical Layer
      • Physical Layer Architecture
      • Reverse Parallel Loopback
    • PCI Express Avalon-MM Bridge
      • Avalon-MM-to-PCI Express Write Requests
      • Avalon-MM-to-PCI Express Upstream Read Requests
      • PCI Express-to-Avalon-MM Read Completions
      • PCI Express-to-Avalon-MM Downstream Write Requests
      • PCI Express-to-Avalon-MM Downstream Read Requests
      • Avalon-MM-to-PCI Express Read Completions
      • PCI Express-to-Avalon-MM Address Translation
      • Avalon-MM-to-PCI Express Address Translation
      • Generation of PCI Express Interrupts
      • Generation of Avalon-MM Interrupts
    • Completer Only PCI Express Endpoint Single DWord
      • IP Compiler for PCI Express RX Block
      • Avalon-MM RX Master Block
      • IP Compiler for PCI Express TX Block
      • Interrupt Handler Block
  • 5. IP Core Interfaces
    • Avalon-ST Interface
      • 64- or 128-Bit Avalon-ST RX Port
      • 64- or 128-Bit Avalon-ST TX Port
      • Mapping of Avalon-ST Packets to PCI Express TLPs
      • Root Port Mode Configuration Requests
      • ECRC Forwarding
      • Clock Signals—Hard IP Implementation
      • Clock Signals—Soft IP Implementation
      • Reset and Link Training Signals
        • Reset Details
      • ECC Error Signals
      • PCI Express Interrupts for Endpoints
      • PCI Express Interrupts for Root Ports
      • Configuration Space Signals—Hard IP Implementation
        • Configuration Space Register Access Timing
        • Configuration Space Register Access
      • Configuration Space Signals—Soft IP Implementation
      • LMI Signals—Hard IP Implementation
        • LMI Read Operation
        • LMI Write Operation
      • IP Core Reconfiguration Block Signals—Hard IP Implementation
      • Power Management Signals
      • Completion Side Band Signals
    • Avalon-MM Application Interface
      • 32-Bit Non-Bursting Avalon-MM CRA Slave Signals
      • RX Avalon-MM Master Signals
      • 64-Bit Bursting TX Avalon-MM Slave Signals
      • Clock Signals
      • Reset and Status Signals
    • Physical Layer Interface Signals
      • Transceiver Control Signals
      • Serial Interface Signals
      • PIPE Interface Signals
    • Test Signals
      • Test Interface Signals—Hard IP Implementation
      • Test Interface Signals—Soft IP Implementation
      • Avalon-ST Test Signals
  • 6. Register Descriptions
    • Configuration Space Register Content
    • PCI Express Avalon-MM Bridge Control Register Content
      • Avalon-MM to PCI Express Interrupt Registers
      • PCI Express Mailbox Registers
      • Avalon-MM-to-PCI Express Address Translation Table
      • PCI Express to Avalon-MM Interrupt Status and Enable Registers
      • Avalon-MM Mailbox Registers
    • Comprehensive Correspondence between Config Space Registers and PCIe Spec Rev 2.0
  • 7. Reset and Clocks
    • Reset Hard IP Implementation
      • <variant>_plus.v or .vhd
      • <variant>.v or .vhd
    • Reset Soft IP Implementation
    • Clocks
      • Avalon-ST Interface—Hard IP Implementation
        • p_clk
        • core_clk, core_clk_out
        • pld_clk
      • Avalon-ST Interface—Soft IP Implementation
        • 100 MHz Reference Clock and 125 MHz Application Clock
        • 100 MHz Reference Clock and 250 MHz Application Clock
        • Clocking for a Generic PIPE PHY and the Simulation Testbench
      • Avalon-MM Interface–Hard IP and Soft IP Implementations
  • 8. Transaction Layer Protocol (TLP) Details
    • Supported Message Types
    • Transaction Layer Routing Rules
    • Receive Buffer Reordering
  • 9. Optional Features
    • ECRC
      • ECRC on the RX Path
      • ECRC on the TX Path
    • Active State Power Management (ASPM)
      • Exit Latency
      • Acceptable Latency
    • Lane Initialization and Reversal
    • Instantiating Multiple IP Compiler for PCI Express Instances
      • Clock and Signal Requirements for Devices with Transceivers
      • Source Multiple Tcl Scripts
  • 10. Interrupts
    • PCI Express Interrupts for Endpoints
    • MSI Interrupts
    • MSI-X
    • Legacy Interrupts
    • PCI Express Interrupts for Root Ports
  • 11. Flow Control
    • Throughput of Posted Writes
    • Throughput of Non-Posted Reads
  • 12. Error Handling
    • Physical Layer Errors
    • Data Link Layer Errors
    • Transaction Layer Errors
    • Error Reporting and Data Poisoning
    • Uncorrectable and Correctable Error Status Bits
  • 13. Reconfiguration and Offset Cancellation
    • Dynamic Reconfiguration
    • Transceiver Offset Cancellation
  • 14. External PHYs
    • External PHY Support
      • 16-bit SDR Mode
      • 16-bit SDR Mode with a Source Synchronous TXClk
      • 8-bit DDR Mode
      • 8-bit DDR with a Source Synchronous TXClk
      • 8-bit SDR Mode
      • 8-bit SDR with a Source Synchronous TXClk
      • 16-bit PHY Interface Signals
      • 8-bit PHY Interface Signals
    • Selecting an External PHY
    • External PHY Constraint Support
  • 15. Testbench and Design Example
    • Endpoint Testbench
    • Root Port Testbench
    • Chaining DMA Design Example
      • Design Example BAR/Address Map
      • Chaining DMA Control and Status Registers
      • Chaining DMA Descriptor Tables
    • Test Driver Module
      • DMA Write Cycles
      • DMA Read Cycles
    • Root Port Design Example
    • Root Port BFM
      • BFM Memory Map
      • Configuration Space Bus and Device Numbering
      • Configuration of Root Port and Endpoint
      • Issuing Read and Write Transactions to the Application Layer
    • BFM Procedures and Functions
      • BFM Read and Write Procedures
        • ebfm_barwr Procedure
        • ebfm_barwr_imm Procedure
        • ebfm_barrd_wait Procedure
        • ebfm_barrd_nowt Procedure
        • ebfm_cfgwr_imm_wait Procedure
        • ebfm_cfgwr_imm_nowt Procedure
        • ebfm_cfgrd_wait Procedure
        • ebfm_cfgrd_nowt Procedure
      • BFM Configuration Procedures
        • ebfm_cfg_rp_ep Procedure
        • ebfm_cfg_decode_bar Procedure
      • BFM Shared Memory Access Procedures
        • Shared Memory Constants
        • shmem_write
        • shmem_read Function
        • shmem_display VHDL Procedure or Verilog HDL Function
        • shmem_fill Procedure
        • shmem_chk_ok Function
      • BFM Log and Message Procedures
        • Log Constants
        • ebfm_display VHDL Procedure or Verilog HDL Function
        • ebfm_log_stop_sim VHDL Procedure or Verilog HDL Function
        • ebfm_log_set_suppressed_msg_mask Procedure
        • ebfm_log_set_stop_on_msg_mask Procedure
        • ebfm_log_open Procedure
        • ebfm_log_close Procedure
      • VHDL Formatting Functions
        • himage (std_logic_vector) Function
        • himage (integer) Function
      • Verilog HDL Formatting Functions
        • himage1
        • himage2
        • himage4
        • himage8
        • himage16
        • dimage1
        • dimage2
        • dimage3
        • dimage4
        • dimage5
        • dimage6
        • dimage7
      • Procedures and Functions Specific to the Chaining DMA Design Example
        • chained_dma_test Procedure
        • dma_rd_test Procedure
        • dma_wr_test Procedure
        • dma_set_rd_desc_data Procedure
        • dma_set_wr_desc_data Procedure
        • dma_set_header Procedure
        • rc_mempoll Procedure
        • msi_poll Procedure
        • dma_set_msi Procedure
        • find_mem_bar Procedure
        • dma_set_rclast Procedure
        • ebfm_display_verb Procedure
  • 16. Qsys Design Example
    • Creating a Quartus II Project
    • Running Qsys
    • Parameterizing the IP Compiler for PCI Express
    • Adding the Remaining Components to the Qsys System
    • Completing the Connections in Qsys
    • Specifying Exported Interfaces
    • Specifying Address Assignments
    • Generating the Qsys System
    • Simulating the Qsys System
      • Changing from PIPE Mode to Serial Mode
      • Running Simulation
    • Preparing the Design for Compilation
      • Design Example Wrapper File
      • Adding Files to your Quartus II Project
    • Compiling the Design
    • Programming a Device
  • 17. Debugging
    • Hardware Bring-Up Issues
      • Link Training
        • Debugging Link Training Issues Using Quartus II SignalTap II Logic Analyzer
        • Use Third-Party PCIe Analyzer
      • BIOS Enumeration Issues
      • Configuration Space Settings
    • Link and Transceiver Testing
  • A. Transaction Layer Packet (TLP) Header Formats
    • TLP Packet Format without Data Payload
    • TLP Packet Format with Data Payload
  • B. IP Compiler for PCI Express Core with the Descriptor/Data Interface
    • Descriptor/Data Interface
      • Receive Datapath Interface Signals
        • Transaction Examples Using Receive Signals
      • Transmit Operation Interface Signals
        • Transmit Datapath Interface Signals
        • Transaction Examples Using Transmit Signals
      • Completion Interface Signals for Descriptor/Data Interface
    • Incremental Compile Module for Descriptor/Data Examples
      • ICM Features
      • ICM Functional Description
        • <variation_name>_icm Partition
        • ICM Block Diagram
        • ICM Files
        • ICM Application-Side Interface
    • Recommended Incremental Compilation Flow
  • C. Performance and Resource Utilization Soft IP Implementation
    • Avalon-ST Interface
      • Arria GX Devices
      • Arria II GX Devices
      • Stratix II GX Devices
      • Stratix III Family
      • Stratix IV Family
    • Avalon-MM Interface
    • Descriptor/Data Interface
      • Arria GX Devices
      • Cyclone III Family
      • Stratix II GX Devices
      • Stratix III Family
      • Stratix IV Family
  • Additional Information
    • Revision History
    • How to Contact Altera
    • Typographic Conventions