Document Outline

• Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
• Contents
• 1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function
  • Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features
  • Low Latency 40-100GbE IP Core Device Family and Speed Grade Support
    • Device Family Support
    • Low Latency 40-100GbE IP Core Device Speed Grade Support
  • IP Core Verification
    • Simulation Environment
    • Compilation Checking
    • Hardware Testing
  • Performance and Resource Utilization
    • Stratix V Resource Utilization for Low Latency 40-100GbE IP Cores
    • Arria 10 Resource Utilization for Low Latency 40-100GbE IP Cores
  • Release Information
• 2. Getting Started
  • Installation and Licensing for LL 40-100GbE IP Core for Stratix V Devices
  • Installing and Licensing IP Cores
    • OpenCore Plus IP Evaluation
  • Specifying the Low Latency 40-100GbE IP Core Parameters and Options
  • IP Core Parameters
  • Files Generated for Stratix V Variations
  • Files Generated for Arria 10 Variations
  • Integrating Your IP Core in Your Design
    • Pin Assignments
    • External Transceiver Reconfiguration Controller Required in Stratix V Designs
    • External Transceiver PLL Required in Arria 10 Designs
    • External Time-of-Day Module for Variations with 1588 PTP Feature
    • Clock Requirements for 40GBASE-KR4 Variations
    • External TX MAC PLL
    • Placement Settings for the Low Latency 40-100GbE IP Core
  • Low Latency 40-100GbE IP Core Testbenches
    • Low Latency 40-100GbE IP Core Testbench Overview
    • Understanding the Testbench Behavior
  • Simulating the Low Latency 40‑100GbE IP Core With the Testbenches
    • Generating the Low Latency 40-100GbE Testbench
    • Optimizing the Low Latency 40‑100GbE IP Core Simulation With the Testbenches
    • Simulating with the Modelsim Simulator
    • Simulating with the NCSim Simulator
    • Simulating with the VCS Simulator
    • Testbench Output Example: Low Latency 40-100GbE IP Core
  • Compiling the Full Design and Programming the FPGA
  • Initializing the IP Core
• 3. Functional Description
  • High Level System Overview
  • Low Latency 40-100GbE MAC and PHY Functional Description
    • Low Latency 40-100GbE IP Core TX Datapath
      • Preamble, Start, and SFD Insertion
      • Address Insertion
      • Length/Type Field Processing
      • Frame Padding
      • Frame Check Sequence (CRC-32) Insertion
      • Inter‑Packet Gap Generation and Insertion
      • Error Insertion Test and Debug Feature
    • Low Latency 40-100GbE IP Core TX Data Bus Interfaces
      • Low Latency 40-100GbE IP Core User Interface Data Bus
      • Low Latency 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface)
      • Low Latency 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface)
      • Bus Quantization Effects With Adapters
      • User Interface to Ethernet Transmission
        • Order of Transmission
    • Low Latency 40-100GbE IP Core RX Datapath
      • Low Latency 40-100GbE IP Core RX Filtering
      • 40-100GbE IP Core Preamble Processing
      • 40-100GbE IP Core FCS (CRC-32) Removal
      • 40-100GbE IP Core CRC Checking
      • LL 40-100GbE IP Core Malformed Packet Handling
      • RX CRC Forwarding
      • Inter-Packet Gap
      • Pause Ignore
      • Control Frame Identification
    • Low Latency 40-100GbE IP Core RX Data Bus Interface
      • Low Latency 40-100GbE IP Core User Interface Data Bus
      • Low Latency 40-100GbE IP Core RX Data Bus
      • Low Latency 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
    • Low Latency 100GbE CAUI–4 PHY
    • External Reconfiguration Controller
    • External Transceiver PLL
    • External TX MAC PLL
    • Congestion and Flow Control Using Pause Frames
      • Conditions Triggering XOFF Frame Transmission
      • Conditions Triggering XON Frame Transmission
    • Pause Control and Generation Interface
    • Pause Control Frame Filtering
    • Link Fault Signaling Interface
    • Statistics Counters Interface
      • OctetOK Count Interface
    • 1588 Precision Time Protocol Interfaces
      • Implementing a 1588 System That Includes a LL 40-100GbE IP Core
      • PTP Receive Functionality
      • PTP Transmit Functionality
      • External Time-of-Day Module for 1588 PTP Variations
      • 1588 PTP Interface Signals
      • PTP Timestamp Formats
    • PHY Status Interface
    • Transceiver PHY Serial Data Interface
    • Low Latency 40GBASE-KR4 IP Core Variations
    • Control and Status Interface
    • Arria 10 Transceiver Reconfiguration Interface
    • Clocks
    • Resets
  • Signals
    • Low Latency 40-100GbE IP Core Signals
  • Software Interface: Registers
    • Low Latency 40-100GbE IP Core Registers
      • PHY Registers
      • Link Fault Signaling Registers
      • LL 40GBASE-KR4 Registers
      • Low Latency 40-100GbE IP Core MAC Configuration Registers
      • Pause Registers
      • TX Statistics Registers
      • RX Statistics Registers
      • 1588 PTP Registers
  • Ethernet Glossary
• 4. Debugging the 40GbE and 100GbE Link
• A. Low Latency 40-100GbE IP Core Example Project
  • Connections in the Low Latency 40-100GbE IP Core Example Project
  • Generating the Low Latency 40-100GbE Example Project
  • Compiling the Low Latency 40-100GbE IP Core Example Project
• B. Arria 10 10GBASE-KR Registers
  • 10GBASE-KR PHY Register Definitions
• C. Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v15.0
• D. Additional Information
  • Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History
  • How to Contact Altera
  • Typographic Conventions