Document Outline

• PCI Compiler User Guide
  • Contents
  • About PCI Compiler
    • Introduction
    • Release Information
    • Device Family Support
    • Features
      • Common Features
      • PCI Compiler with MegaWizard Plug-in Manager Flow
      • PCI Compiler with SOPC Builder Flow
    • General Description
      • PCI MegaCore Functions
      • PCI Testbench
      • PCI Compiler with MegaWizard Plug-in Manager Flow
      • PCI Compiler With SOPC Builder Flow
    • Selecting the Appropriate Flow for Your Design
      • PCI Compiler With SOPC Builder Flow
        • Advantages
        • Disadvantages
      • PCI Compiler With MegaWizard Plug-in Manager Flow
        • Advantages
        • Disadvantages
    • Compliance Summary
    • Performance and Resource Utilization
      • PCI Compiler with MegaWizard Plug-in Manager Flow
      • PCI Compiler with SOPC Builder Flow
    • Installation and Licensing
      • OpenCore Plus Evaluation
      • OpenCore Plus Time-Out Behavior
  • Section I. PCI Compiler With MegaWizard Plug-In Manager Flow
    • 1. Getting Started
      • Design Flow
      • PCI MegaCore Function Design Walkthrough
        • Create a New Quartus II Project
        • Launch IP Toolbench
        • Step 1: Parameterize
        • Step 2: Set Up Simulation
        • Step 3: Generate
      • Simulate the Design
        • Simulation in the Quartus II Software
      • The Quartus II Simulation Files
        • Master Simulation Files
        • Target Simulation Files
      • Compile the Design
      • Program a Device
      • PCI Timing Support
      • Using the Reference Designs
        • pci_mt32 MegaCore Function Reference Design
          • Synthesis & Compilation Instructions
        • pci_mt64 MegaCore Function Reference Design
          • synthesis & Compilation Instructions
    • 2. Parameter Settings
      • Parameterize PCI Compiler
      • PCI MegaCore Function Settings
      • Read-Only PCI Configuration Registers
      • PCI Base Address Registers (BARs)
      • Advanced PCI MegaCore Function Features
        • Optional Registers
        • Optional Interrupt Capabilities
        • Master Features
          • Allow Variable Byte Enables During Burst Transactions
          • Use in Host Bridge Application
          • Allow Internal Arbitration Logic
          • Disable Master Latency Timer
          • Assume ack64n Response
      • Variation File Parameters
    • 3. Functional Description
      • Functional Overview
        • Target Device Signals & Signal Assertion
        • Master Device Signals & Signal Assertion
      • PCI Bus Signals
        • Parameterized Configuration Register Signals
        • Local Address, Data, Command, & Byte Enable Signals
        • Target Local-Side Signals
        • Master Local-Side Signals
      • PCI Bus Commands
      • Configuration Registers
        • Vendor ID Register
        • Device ID Register
        • Command Register
        • Status Register
        • Revision ID Register
        • Class Code Register
        • Cache Line Size Register
        • Latency Timer Register
        • Header Type Register
        • Base Address Registers
        • CardBus CIS Pointer Register
        • Subsystem Vendor ID Register
        • Subsystem ID Register
        • Expansion ROM Base Address Register
        • Capabilities Pointer
        • Interrupt Line Register
        • Interrupt Pin Register
        • Minimum Grant Register
        • Maximum Latency Register
      • Target Mode Operation
        • Target Read Transactions
          • Memory Read Transactions
            • Single-cycle Memory Read Target Transactions
            • Burst Memory Read Target Transactions
            • Mismatched Bus Width Memory Read Target Transactions
          • I/O Read Transactions
          • Configuration Read Transactions
        • Target Write Transactions
          • Memory Write Transactions
            • Single-cycle Memory Write Target Transactions
            • Burst Memory Write Target Transactions
            • Mismatched Bus-Width Memory Write Target Transactions
          • I/O Write Transactions
          • Configuration Write Transactions
        • Target Transaction Terminations
          • Retry
          • Disconnect
          • Target Abort
        • Additional Design Guidelines for Target Transactions
      • Master Mode Operation
        • PCI Bus Parking
          • Design Consideration
        • Master Read Transactions
          • Memory Read Transactions
            • Burst Memory Read Master Transactions
            • Single-Cycle Memory Read Master Transaction
            • Mismatched Bus Width Burst Memory Read Master Transactions
          • I/O & Configuration Read Transactions
        • Master Write Transactions
          • Memory Write Transactions
            • Burst Memory Write Master Transactions
            • Burst Memory Write Master Transactions with Variable Byte Enables
            • 32-Bit Single-Cycle Memory Write Master Transactions
            • 64-Bit Single Cycle Memory Write Master Transactions
            • Mismatched Bus Width Burst Memory Write Master Transactions
          • I/O & Configuration Write Master Transactions
        • Abnormal Master Transaction Termination
          • Latency Timer Expires
          • Retry
          • Disconnect Without Data
          • Disconnect with Data
          • Target Abort
          • Master Abort
      • Host Bridge Operation
        • Using the PCI MegaCore Function as a Host Bridge
          • PCI Configuration Read Transaction from the pci_mt64 Local Master Device to the Internal Configuration Space
          • PCI Configuration Write Transaction from the pci_mt64 Local Master Device to the Internal Configuration Space
      • 64-Bit Addressing, Dual Address Cycle (DAC)
        • Target Mode Operation
          • 64-Bit Address, 64-Bit Data Single-Cycle Target Read Transaction
        • Master Mode Operation
          • 64-Bit Address, 64-Bit Data Master Burst Memory Read Transaction
    • 4. Testbench
      • General Description
      • Features
      • PCI Testbench Files
      • Testbench Specifications
        • Master Transactor (mstr_tranx)
          • PROCEDURES and TASKS Sections
          • INITIALIZATION Section
          • USER COMMANDS Section
            • cfg_rd
            • cfg_wr
            • mem_wr_32
            • mem_rd_32
            • mem_wr_64
            • mem_rd_64
            • io_wr
            • io_rd
          • Target Transactor (trgt_tranx)
          • FILE IO section
          • PROCEDURES and TASKS sections
        • Bus Monitor (monitor)
        • Clock Generator (clk_gen)
        • Arbiter (arbiter)
        • Pull Up (pull_up)
      • Local Reference Design
        • Local Target
        • DMA Engine
        • Local Master
        • lm_lastn Generator
        • Prefetch
        • LPM RAM
      • Simulation Flow
  • Section II. PCI Compiler With SOPC Builder Flow
    • 5. Getting Started
      • Design Flow
      • PCI Compiler with SOPC Builder Flow Design Walkthrough
        • Create a New Quartus II Project
        • Set Up the PCI-Avalon Bridge
        • Add the Remaining Components to the SOPC Builder System
        • Complete the Connections in SOPC Builder
        • Generate the SOPC Builder System
        • Files Generated by SOPC Builder
      • Simulate the Design
      • Compile the Design
      • Program a Device
      • Upgrading Systems from a Previous Version
    • 6. Parameter Settings
      • System Options-1
        • PCI Device Mode
          • PCI Master/Target Peripheral
          • PCI Target-Only Peripheral
          • PCI Host-Bridge Device
        • PCI Target Performance
          • Single-Cycle Transfers Only
          • Burst Transfers with Single Pending Read
          • Burst Transfers with Multiple Pending Reads
          • Maximum Target Read Burst Size
        • PCI Master Performance
          • Burst Transfers with Single Pending Read
          • Burst Transfers with Multiple Pending Reads
      • Value of Multiple Pending Reads
      • System Options-2
        • PCI Bus Speed
        • PCI Data Bus Width
        • PCI Clock/Reset Settings
        • PCI Bus Arbiter
      • PCI Configuration
        • PCI Base Address Registers
        • PCI Read-Only Registers
        • Setting the PCI Base Address Register Values
        • Manual Setting of the BAR Size & Avalon Base Address
      • Avalon Configuration
    • 7. Functional Description
      • Functional Overview
        • PCI-Avalon Bridge Blocks
          • Avalon-MM Ports
            • Prefetchable Avalon-MM Master
            • Non-Prefetchable Avalon-MM Master
            • PCI Bus Access Slave
            • Control Register Access Avalon-MM Slave
          • Control/Status Register Module
            • Mailbox Registers
          • PCI MegaCore Function
          • PCI Bus Arbiter
          • Other PCI-Avalon Bridge Modules
        • PCI Operational Modes
          • PCI Target-Only Peripheral Mode Operation
          • PCI Master/Target Peripheral Mode Operation
            • Control Register Access Avalon Slave
          • PCI Host-Bridge Device Mode Operation
        • Performance Profiles
          • Target Performance
            • Single-Cycle Transfers Only
            • Burst Transfers With Single Pending Read
            • Burst Transfers With Multiple Pending Reads
          • Master Performance
            • Burst Transfers With Single Pending Read
            • Burst Transfers With Multiple Pending Reads
      • Interface Signals
        • PCI Bus Arbiter Signals
      • PCI Bus Commands
      • PCI Target Operation
        • Non-Prefetchable Operations
          • Non-Prefetchable Write Operations
          • I/O Write Operations
          • Non-Prefetchable Read Operations
        • Prefetchable Operations
          • Prefetchable Write Operations
          • Prefetchable Read Operations
        • PCI-to-Avalon Address Translation
      • PCI Master Operation
        • Avalon-To-PCI Read & Write Operation
          • Avalon-to-PCI Write Requests
          • Avalon-to-PCI Read Requests
          • Arbitration Among Pending PCI Master Requests
        • Avalon-to-PCI Address Translation
        • Ordering of Requests
          • Ordering of Avalon-to-PCI Operations
          • Ordering PCI-to-Avalon Operations
      • PCI Host-Bridge Operation
      • Altera-Provided PCI Bus Arbiter
      • Interrupts
        • Generation of PCI Interrupts
        • Reception of PCI Interrupts
        • Generation of Avalon-MM Interrupts
      • Control & Status Registers
        • PCI Interrupt Status Register
        • PCI Interrupt Enable Register
        • PCI Mailbox Register Access
        • Avalon-to-PCI Address Translation Table
        • Read-Only Configuration Registers
        • Avalon-MM Interrupt Status Register
        • Avalon-MM Interrupt Enable Register
        • Avalon Mailbox Register Access
    • 8. Testbench
      • General Description
      • Features
      • PCI Testbench Files
      • Testbench Specifications
        • Master Transactor (mstr_tranx)
          • PROCEDURES and TASKS Sections
          • INITIALIZATION Section
          • USER COMMANDS Section
          • cfg_rd
          • cfg_wr
          • mem_wr_32
          • mem_rd_32
          • mem_wr_64
          • mem_rd_64
          • io_wr
          • io_rd
        • Target Transactor (trgt_tranx)
          • FILE IO section
          • PROCEDURES and TASKS sections
        • Bus Monitor (monitor)
        • Arbiter (arbiter)
        • Pull Up (pull_up)
      • Simulation Flow
  • Appendix A. Using PCI Constraint File Tcl Scripts
    • Introduction
    • PCI Constraint Files
    • Simultaneous Switching Noise (SSN) Considerations
    • Additional Options
      • -speed
      • -no_compile
      • -no_pinouts
      • -pin_prefix
      • -pin_suffix
      • -help
    • Upgrading Assignments from a Previous Version of PCI Compiler
      • Upgrading PCI Assignments Containing Nondefault PCI Pin Names
  • Additional Information
    • How to Contact Altera
    • Typographic Conventions