Document Outline

• DecemberPOS-PHY Level 4 IP Core User Guide
  • 1. About This IP Core
    • Release Information
    • Device Family Support
    • Features
    • General Description
      • Interfaces & Protocols
        • SPI-4.2 Interface
        • Atlantic Interface
        • Avalon-MM Interface
    • IP Core Verification
    • Performance and Resource Utilization
    • Installing and Licensing IP Cores
      • OpenCore Plus IP Evaluation
  • 2. Getting Started
    • Design Flow
    • IP Catalog and Parameter Editor
    • Using the Parameter Editor
    • Upgrading Outdated IP Cores
      • Upgrading IP Cores at the Command Line
    • Specify Parameters
    • Files Generated for Altera IP Cores (Legacy Parameter Editor)
    • Simulate the Design
      • Use the Testbench with the ModelSim Simulator
      • Use the Testbench with NativeLink
    • Compile the Design and Program a Device
  • 3. Parameter Settings
    • Basic Parameters
      • Device Family
      • LVDS Data Rate
      • PLL Input Frequency
      • Data Path Width
      • Buffer Mode
      • Atlantic FIFO Buffer Clock
      • Atlantic Interface Width
    • Optional Features
      • Transmitter Options
      • Receiver Options
      • FIFO RAM Blocks
    • Protocol Parameters
      • Calendar Options
      • Transmitter Options
      • Receiver Options
  • 4. Functional Description—Receiver
    • Features
    • Block Description
      • Data Receiver and Serial-to-Parallel Converter (rx_data_phy_altlvds)
      • DPA Channel Aligner (rx_data_phy_dpa)
        • ALTLVDS_RX IP Core
        • Channel Aligner
        • 8:4 Serializer
      • Data Processor (rx_data_proc)
        • Control Word Processing & DIP-4
        • Clock-Domain Crossing Buffer
        • SOP Alignment & Atlantic Conversion
      • Atlantic Buffers
        • Shared Buffer with Embedded Addressing
        • Individual Buffers
      • Status Processor
    • Clock Structure
      • Single Clock Mode
      • Multiple Clock Mode
      • Requirements for rxsys_clk
    • Reset Structure
    • Error Flagging and Handling
      • SPI-4.2 Protocol Errors
      • DIP-4 Marking
        • Optimistic Mode
        • Pessimistic Mode
      • DIP-4 Out of Service Indication
      • Atlantic Interface Error Detection and Handling
        • Missing SOP
        • Missing EOP
    • Signals
    • Avalon-MM Interface Register Map
    • Latency Information
  • 5. Functional Description—Transmitter
    • Features
    • Block Description
      • Atlantic Buffers
        • Shared Buffer with Embedded Addressing
        • Individual Buffers
      • Individual Buffers Transmit Scheduler (tx_sched)
      • Data Processor (tx_data_proc)
        • Atlantic Conversion
        • Control Word Insertion, DIP-4, and Training Pattern Insertion
      • Parallel to Serial Converter (tx_data_phy_altlvds)
      • Status Processor
        • Status Channel Interpretation Modes
        • Status Bypass Port
    • Clock Structure
      • Single Clock Domain
      • Multiple Clock Domain
    • Reset Structure
    • Error Flagging and Handling
      • SPI-4.2 Error Detection and Handling
      • Atlantic Interface Error Detection and Handling
        • Missing SOP
        • Missing EOP
    • Signals
    • Avalon-MM Interface Register Map
    • Latency Information
  • 6. Testbench
    • Receiver Testbench Description
    • Receiver Testbench Examples
    • Transmitter Testbench Description
  • A. Start-Up Sequence
    • Troubleshooting
      • Issues and Tips—Transmitter
      • Issues and Tips—Receiver
      • Issues and Tips—Miscellaneous
  • B. Sharing PLLs for Multicore Designs
  • C. Optimum Frequency for rxsys_clk
  • D. Board Design
    • Pin Constraints
    • Board Design Configuration
    • Design for Testability
      • Probe Points
        • Receiver IP Cores
        • Transmitter IP Cores
      • Spare Pins
      • JTAG Scan Chain
  • E. Programming the SPI-4.2 Calendar via the Avalon Memory-Mapped Interface
    • Introduction
    • Programming the SPI-4.2 Calendar
  • F. Static and Dynamic Phase Alignment
    • Static Alignment
    • Dynamic Alignment
    • Altera Solutions
      • Static Alignment
      • Dynamic Phase Alignment (DPA)
    • AC Timing Analysis
  • G. Conversion from v2.2.x
    • Introduction
    • Receiver Signals
    • Transmitter Signals
  • Additional Information
    • Document Revision History
    • How to Contact Altera
    • Typographic Conventions