Altera Quartus II Settings File Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for Quartus II Settings File Altera
Manuals
| Recognized languages: | English |
|---|---|
| Pages: | 1344 |
| Size: | 3.89 MB |
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Document Outline
- Quartus Settings File Reference Manual
- Advanced I/O Timing Assignments
- BOARD_MODEL_EBD_FAR_END
- BOARD_MODEL_EBD_FILE_NAME
- BOARD_MODEL_EBD_SIGNAL_NAME
- BOARD_MODEL_FAR_C
- BOARD_MODEL_FAR_DIFFERENTIAL_R
- BOARD_MODEL_FAR_PULLDOWN_R
- BOARD_MODEL_FAR_PULLUP_R
- BOARD_MODEL_FAR_SERIES_R
- BOARD_MODEL_NEAR_C
- BOARD_MODEL_NEAR_DIFFERENTIAL_R
- BOARD_MODEL_NEAR_PULLDOWN_R
- BOARD_MODEL_NEAR_PULLUP_R
- BOARD_MODEL_NEAR_SERIES_R
- BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH
- BOARD_MODEL_NEAR_TLINE_LENGTH
- BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH
- BOARD_MODEL_TERMINATION_V
- BOARD_MODEL_TLINE_C_PER_LENGTH
- BOARD_MODEL_TLINE_LENGTH
- BOARD_MODEL_TLINE_L_PER_LENGTH
- ENABLE_ADVANCED_IO_TIMING
- OUTPUT_IO_TIMING_ENDPOINT
- OUTPUT_IO_TIMING_FAR_END_VMEAS
- OUTPUT_IO_TIMING_NEAR_END_VMEAS
- PCB_LAYER
- PCB_LAYERS
- PCB_LAYER_THICKNESS
- SYNCHRONOUS_GROUP
- Analysis & Synthesis Assignments
- ADV_NETLIST_OPT_ALLOWED
- ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
- ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION
- ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION
- ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION
- ALLOW_CHILD_PARTITIONS
- ALLOW_POWER_UP_DONT_CARE
- ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES
- ALLOW_SYNCH_CTRL_USAGE
- ALLOW_XOR_GATE_USAGE
- APEX20K_OPTIMIZATION_TECHNIQUE
- APEX20K_TECHNOLOGY_MAPPER
- AUTO_CARRY_CHAINS
- AUTO_CASCADE_CHAINS
- AUTO_CLOCK_ENABLE_RECOGNITION
- AUTO_DSP_RECOGNITION
- AUTO_ENABLE_SMART_COMPILE
- AUTO_GLOBAL_CLOCK_MAX
- AUTO_GLOBAL_OE_MAX
- AUTO_IMPLEMENT_IN_ROM
- AUTO_LCELL_INSERTION
- AUTO_OPEN_DRAIN_PINS
- AUTO_PARALLEL_EXPANDERS
- AUTO_PARALLEL_SYNTHESIS
- AUTO_RAM_BLOCK_BALANCING
- AUTO_RAM_RECOGNITION
- AUTO_RAM_TO_LCELL_CONVERSION
- AUTO_RESOURCE_SHARING
- AUTO_ROM_RECOGNITION
- AUTO_SHIFT_REGISTER_RECOGNITION
- BLOCK_DESIGN_NAMING
- CARRY_CHAIN_LENGTH
- CASCADE_CHAIN_LENGTH
- CLKLOCKX1_INPUT_FREQ
- CYCLONEII_OPTIMIZATION_TECHNIQUE
- CYCLONE_OPTIMIZATION_TECHNIQUE
- DEVICE_FILTER_PACKAGE
- DEVICE_FILTER_PIN_COUNT
- DEVICE_FILTER_SPEED_GRADE
- DEVICE_FILTER_VOLTAGE
- DISABLE_DSP_NEGATE_INFERENCING
- DISABLE_OCP_HW_EVAL
- DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES
- DONT_MERGE_REGISTER
- DQS_DELAY
- DQS_FREQUENCY
- DQS_SHIFT
- DQS_SYSTEM_CLOCK
- DSE_SYNTH_EXTRA_EFFORT_MODE
- DSP_BLOCK_BALANCING
- EDA_DESIGN_ENTRY_SYNTHESIS_TOOL
- EDA_INPUT_DATA_FORMAT
- EDA_INPUT_GND_NAME
- EDA_INPUT_VCC_NAME
- EDA_LMF_FILE
- EDA_RUN_TOOL_AUTOMATICALLY
- EDA_SHOW_LMF_MAPPING_MESSAGES
- EDA_VHDL_LIBRARY
- ENABLE_IP_DEBUG
- ENABLE_M512
- EXTRACT_VERILOG_STATE_MACHINES
- EXTRACT_VHDL_STATE_MACHINES
- FAMILY
- FLEX10K_CARRY_CHAIN_LENGTH
- FLEX10K_OPTIMIZATION_TECHNIQUE
- FLEX6K_CARRY_CHAIN_LENGTH
- FLEX6K_OPTIMIZATION_TECHNIQUE
- FORCE_SYNCH_CLEAR
- HDL_INITIAL_FANOUT_LIMIT
- HDL_MESSAGE_LEVEL
- HDL_MESSAGE_OFF
- HDL_MESSAGE_ON
- HPS_PARTITION
- IGNORE_CARRY_BUFFERS
- IGNORE_CASCADE_BUFFERS
- IGNORE_GLOBAL_BUFFERS
- IGNORE_LCELL_BUFFERS
- IGNORE_MAX_FANOUT_ASSIGNMENTS
- IGNORE_ROW_GLOBAL_BUFFERS
- IGNORE_SOFT_BUFFERS
- IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF
- IGNORE_VERILOG_INITIAL_CONSTRUCTS
- IMPLEMENT_AS_CLOCK_ENABLE
- IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL
- INFER_RAMS_FROM_RAW_LOGIC
- IP_SEARCH_PATHS
- LCELL_INSERTION
- LIMIT_AHDL_INTEGERS_TO_32_BITS
- MAX7000_FANIN_PER_CELL
- MAX7000_IGNORE_LCELL_BUFFERS
- MAX7000_IGNORE_SOFT_BUFFERS
- MAX7000_OPTIMIZATION_TECHNIQUE
- MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH
- MAXII_OPTIMIZATION_TECHNIQUE
- MAX_AUTO_GLOBAL_REGISTER_CONTROLS
- MAX_BALANCING_DSP_BLOCKS
- MAX_FANOUT
- MAX_LABS
- MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS
- MAX_RAM_BLOCKS_M4K
- MAX_RAM_BLOCKS_M512
- MAX_RAM_BLOCKS_MRAM
- MERCURY_CARRY_CHAIN_LENGTH
- MERCURY_OPTIMIZATION_TECHNIQUE
- MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE
- MUX_RESTRUCTURE
- NOT_GATE_PUSH_BACK
- NUMBER_OF_INVERTED_REGISTERS_REPORTED
- NUMBER_OF_REMOVED_REGISTERS_REPORTED
- NUMBER_OF_SWEPT_NODES_REPORTED
- NUMBER_OF_SYNTHESIS_MIGRATION_ROWS
- OPTIMIZATION_TECHNIQUE
- OPTIMIZE_POWER_DURING_SYNTHESIS
- PARALLEL_EXPANDER_CHAIN_LENGTH
- PARALLEL_SYNTHESIS
- PARAMETER
- POWER_UP_LEVEL
- PRESERVE_FANOUT_FREE_NODE
- PRESERVE_REGISTER
- PRE_MAPPING_RESYNTHESIS
- PRPOF_ID
- RBCGEN_CRITICAL_WARNING_TO_ERROR
- REMOVE_DUPLICATE_REGISTERS
- REMOVE_REDUNDANT_LOGIC_CELLS
- REPORT_CONNECTIVITY_CHECKS
- REPORT_PARAMETER_SETTINGS
- REPORT_SOURCE_ASSIGNMENTS
- RESYNTHESIS_OPTIMIZATION_EFFORT
- RESYNTHESIS_PHYSICAL_SYNTHESIS
- RESYNTHESIS_RETIMING
- SAFE_STATE_MACHINE
- SAVE_DISK_SPACE
- SEARCH_PATH
- SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL
- SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES
- STATE_MACHINE_PROCESSING
- STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT
- STRATIXII_CARRY_CHAIN_LENGTH
- STRATIXII_OPTIMIZATION_TECHNIQUE
- STRATIX_CARRY_CHAIN_LENGTH
- STRATIX_OPTIMIZATION_TECHNIQUE
- STRICT_RAM_RECOGNITION
- SYNCHRONIZATION_REGISTER_CHAIN_LENGTH
- SYNTHESIS_EFFORT
- SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER
- SYNTHESIS_S10_MIGRATION_CHECKS
- SYNTH_CLOCK_MUX_PROTECTION
- SYNTH_GATED_CLOCK_CONVERSION
- SYNTH_MESSAGE_LEVEL
- SYNTH_PROTECT_SDC_CONSTRAINT
- SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM
- SYNTH_TIMING_DRIVEN_SYNTHESIS
- TOP_LEVEL_ENTITY
- TRUE_WYSIWYG_FLOW
- USER_LIBRARIES
- USE_GENERATED_PHYSICAL_CONSTRAINTS
- USE_HIGH_SPEED_ADDER
- USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING
- VERILOG_CONSTANT_LOOP_LIMIT
- VERILOG_INPUT_VERSION
- VERILOG_LMF_FILE
- VERILOG_MACRO
- VERILOG_NON_CONSTANT_LOOP_LIMIT
- VERILOG_SHOW_LMF_MAPPING_MESSAGES
- VHDL_INPUT_LIBRARY
- VHDL_INPUT_VERSION
- VHDL_LMF_FILE
- VHDL_SHOW_LMF_MAPPING_MESSAGES
- Assembler Assignments
- APEX20K_CONFIGURATION_DEVICE
- APEX20K_CONFIG_DEVICE_JTAG_USER_CODE
- APEX20K_JTAG_USER_CODE
- ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE
- AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE
- AUTO_RESTART_CONFIGURATION
- CLOCK_SOURCE
- COMPRESSION_MODE
- CONFIGURATION_CLOCK_DIVISOR
- CONFIGURATION_CLOCK_FREQUENCY
- CYCLONEIII_CONFIGURATION_DEVICE
- CYCLONEII_M4K_COMPATIBILITY
- CYCLONE_CONFIGURATION_DEVICE
- DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE
- ENABLE_ADV_SEU_DETECTION
- ENABLE_AUTONOMOUS_PCIE_HIP
- ENABLE_IO_WEAK_PULL_UP_DURING_CONFIG
- ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
- ENABLE_OCT_DONE
- EN_SPI_IO_WEEK_PULLUP
- EN_USER_IO_WEEK_PULLUP
- EPROM_USE_CHECKSUM_AS_USERCODE
- FLEX10K_CONFIGURATION_DEVICE
- FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE
- FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
- FLEX10K_JTAG_USER_CODE
- FLEX6K_CONFIGURATION_DEVICE
- FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
- GENERATE_HEX_FILE
- GENERATE_RBF_FILE
- GENERATE_TTF_FILE
- HARDCOPYII_POWER_ON_EXTRA_DELAY
- HEXOUT_FILE_COUNT_DIRECTION
- HEXOUT_FILE_START_ADDRESS
- MAX7000S_JTAG_USER_CODE
- MAX7000_JTAG_USER_CODE
- MAX7000_USE_CHECKSUM_AS_USERCODE
- MERCURY_CONFIGURATION_DEVICE
- MERCURY_CONFIG_DEVICE_JTAG_USER_CODE
- MERCURY_JTAG_USER_CODE
- ON_CHIP_BITSTREAM_DECOMPRESSION
- POF_VERIFY_PROTECT
- POR_SCHEME
- RELEASE_CLEARS_BEFORE_TRI_STATES
- RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND
- SECURITY_BIT
- STRATIXII_CONFIGURATION_DEVICE
- STRATIXII_MRAM_COMPATIBILITY
- STRATIX_CONFIGURATION_DEVICE
- STRATIX_CONFIG_DEVICE_JTAG_USER_CODE
- STRATIX_JTAG_USER_CODE
- USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT
- USE_CHECKSUM_AS_USERCODE
- USE_CONFIGURATION_DEVICE
- Assignment Group Assignments
- Classic Timing Assignments
- ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS
- CUT_OFF_IO_PIN_FEEDBACK
- CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS
- CUT_OFF_READ_DURING_WRITE_PATHS
- DEFAULT_HOLD_MULTICYCLE
- DO_COMBINED_ANALYSIS
- EMIF_SOC_PHYCLK_ADVANCE_MODELING
- INPUT_TRANSITION_TIME
- LVDS_FIXED_CLOCK_DATA_PHASE
- MAX_CORE_JUNCTION_TEMP
- MIN_CORE_JUNCTION_TEMP
- NOMINAL_CORE_SUPPLY_VOLTAGE
- PACKAGE_SKEW_COMPENSATION
- PLL_EXTERNAL_FEEDBACK_BOARD_DELAY
- TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT
- TIMEQUEST_DO_CCPP_REMOVAL
- TIMEQUEST_DO_REPORT_TIMING
- TIMEQUEST_MULTICORNER_ANALYSIS
- TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS
- TIMEQUEST_REPORT_SCRIPT
- TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS
- TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS
- USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN
- Compiler Assignments
- Design Assistant Assignments
- ACLK_CAT
- ACLK_RULE_IMSZER_ADOMAIN
- ACLK_RULE_NO_SZER_ACLK_DOMAIN
- ACLK_RULE_SZER_BTW_ACLK_DOMAIN
- CLK_CAT
- CLK_RULE_CLKNET_CLKSPINES
- CLK_RULE_CLKNET_CLKSPINES_THRESHOLD
- CLK_RULE_COMB_CLOCK
- CLK_RULE_GATED_CLK_FANOUT
- CLK_RULE_INPINS_CLKNET
- CLK_RULE_INV_CLOCK
- CLK_RULE_MIX_EDGES
- DA_CUSTOM_RULE_FILE
- DISABLE_DA_GX_RULE
- DISABLE_DA_RULE
- DRC_DEADLOCK_STATE_LIMIT
- DRC_DETAIL_MESSAGE_LIMIT
- DRC_FANOUT_EXCEEDING
- DRC_GATED_CLOCK_FEED
- DRC_REPORT_FANOUT_EXCEEDING
- DRC_REPORT_TOP_FANOUT
- DRC_TOP_FANOUT
- DRC_VIOLATION_MESSAGE_LIMIT
- ENABLE_DA_RULE
- ENABLE_DRC_SETTINGS
- FSM_CAT
- FSM_RULE_DEADLOCK_STATE
- FSM_RULE_NO_RESET_STATE
- FSM_RULE_NO_SZER_ACLK_DOMAIN
- FSM_RULE_UNREACHABLE_STATE
- FSM_RULE_UNUSED_TRANSITION
- HARDCOPY_FLOW_AUTOMATION
- HARDCOPY_NEW_PROJECT_PATH
- HCPY_CAT
- HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES
- HCPY_VREF_PINS
- NONSYNCHSTRUCT_CAT
- NONSYNCHSTRUCT_RULE_ASYN_RAM
- NONSYNCHSTRUCT_RULE_COMBLOOP
- NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE
- NONSYNCHSTRUCT_RULE_DELAY_CHAIN
- NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN
- NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED
- NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR
- NONSYNCHSTRUCT_RULE_REG_LOOP
- NONSYNCHSTRUCT_RULE_RIPPLE_CLK
- NONSYNCHSTRUCT_RULE_SRLATCH
- RESET_CAT
- RESET_RULE_COMB_ASYNCH_RESET
- RESET_RULE_IMSYNCH_ASYNCH_DOMAIN
- RESET_RULE_IMSYNCH_EXRESET
- RESET_RULE_UNSYNCH_ASYNCH_DOMAIN
- RESET_RULE_UNSYNCH_EXRESET
- SIGNALRACE_CAT
- SIGNALRACE_RULE_CLK_PORT_RACE
- SIGNALRACE_RULE_RESET_RACE
- SIGNALRACE_RULE_SECOND_SIGNAL_RACE
- SIGNALRACE_RULE_TRISTATE
- TIMING_CAT
- EDA Netlist Writer Assignments
- EDA_BOARD_BOUNDARY_SCAN_OPERATION
- EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL
- EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL
- EDA_BOARD_DESIGN_SYMBOL_TOOL
- EDA_BOARD_DESIGN_TIMING_TOOL
- EDA_BOARD_DESIGN_TOOL
- EDA_DESIGN_EXTRA_ALTERA_SIM_LIB
- EDA_DESIGN_INSTANCE_NAME
- EDA_ENABLE_GLITCH_FILTERING
- EDA_ENABLE_IPUTF_MODE
- EDA_EXTRA_ELAB_OPTION
- EDA_FLATTEN_BUSES
- EDA_FORMAL_VERIFICATION_ALLOW_RETIMING
- EDA_FORMAL_VERIFICATION_TOOL
- EDA_FV_HIERARCHY
- EDA_GENERATE_FUNCTIONAL_NETLIST
- EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT
- EDA_GENERATE_POWER_INPUT_FILE
- EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT
- EDA_GENERATE_TIMING_CLOSURE_DATA
- EDA_IBIS_MODEL_SELECTOR
- EDA_IBIS_MUTUAL_COUPLING
- EDA_IBIS_SPECIFICATION_VERSION
- EDA_IPFS_FILE
- EDA_LAUNCH_CMD_LINE_TOOL
- EDA_MAINTAIN_DESIGN_HIERARCHY
- EDA_MAP_ILLEGAL_CHARACTERS
- EDA_NATIVELINK_GENERATE_SCRIPT_ONLY
- EDA_NATIVELINK_PORTABLE_FILE_PATHS
- EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT
- EDA_NATIVELINK_SIMULATION_TEST_BENCH
- EDA_NETLIST_WRITER_OUTPUT_DIR
- EDA_RESYNTHESIS_TOOL
- EDA_RTL_SIMULATION_RUN_SCRIPT
- EDA_RTL_SIM_MODE
- EDA_RTL_TEST_BENCH_FILE_NAME
- EDA_RTL_TEST_BENCH_NAME
- EDA_RTL_TEST_BENCH_RUN_FOR
- EDA_SDC_FILE_NAME
- EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED
- EDA_SIMULATION_RUN_SCRIPT
- EDA_SIMULATION_TOOL
- EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE
- EDA_SIMULATION_VCD_OUTPUT_TCL_FILE
- EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME
- EDA_TEST_BENCH_DESIGN_INSTANCE_NAME
- EDA_TEST_BENCH_ENABLE_STATUS
- EDA_TEST_BENCH_ENTITY_MODULE_NAME
- EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB
- EDA_TEST_BENCH_FILE
- EDA_TEST_BENCH_FILE_NAME
- EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY
- EDA_TEST_BENCH_MODULE_NAME
- EDA_TEST_BENCH_NAME
- EDA_TEST_BENCH_RUN_FOR
- EDA_TEST_BENCH_RUN_SIM_FOR
- EDA_TIME_SCALE
- EDA_TIMING_ANALYSIS_TOOL
- EDA_TRUNCATE_LONG_HIERARCHY_PATHS
- EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY
- EDA_VHDL_ARCH_NAME
- EDA_WAIT_FOR_GUI_TOOL_COMPLETION
- EDA_WRITER_DONT_WRITE_TOP_ENTITY
- EDA_WRITE_DEVICE_CONTROL_PORTS
- EDA_WRITE_NODES_FOR_POWER_ESTIMATION
- Equivalence Checker Assignments
- EQC_AUTO_BREAK_CONE
- EQC_AUTO_COMP_LOOP_CUT
- EQC_AUTO_INVERSION
- EQC_AUTO_PORTSWAP
- EQC_AUTO_TERMINATE
- EQC_BBOX_MERGE
- EQC_CONSTANT_DFF_DETECTION
- EQC_DETECT_DONT_CARES
- EQC_DFF_SS_EMULATION
- EQC_DUPLICATE_DFF_DETECTION
- EQC_LVDS_MERGE
- EQC_MAC_REGISTER_UNPACK
- EQC_PARAMETER_CHECK
- EQC_POWER_UP_COMPARE
- EQC_RAM_REGISTER_UNPACK
- EQC_RAM_UNMERGING
- EQC_RENAMING_RULES
- EQC_RENAMING_RULES_LIST
- EQC_SET_PARTITION_BB_TO_VCC_GND
- EQC_SHOW_ALL_MAPPED_POINTS
- EQC_STRUCTURE_MATCHING
- EQC_SUB_CONE_REPORT
- Fitter Assignments
- ACTIVE_SERIAL_CLOCK
- ADCE_ENABLED
- ADVANCED_PHYSICAL_OPTIMIZATION
- ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER
- ALM_REGISTER_PACKING_EFFORT
- ALWAYS_ENABLE_INPUT_BUFFERS
- APEX20KE_DEVICE_IO_STANDARD
- APEX20K_CONFIGURATION_SCHEME
- APEX20K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
- APEX20K_DEVICE_IO_STANDARD
- APEXII_CONFIGURATION_SCHEME
- APEXII_DEVICE_IO_STANDARD
- ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK
- ASYNC_PIPELINE_REG_REACH
- AUTO_C3_M9K_BIT_SKIP
- AUTO_DELAY_CHAINS
- AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS
- AUTO_GLOBAL_CLOCK
- AUTO_GLOBAL_MEMORY_CONTROLS
- AUTO_GLOBAL_OE
- AUTO_GLOBAL_REGISTER_CONTROLS
- AUTO_MERGE_PLLS
- AUTO_PACKED_REGISTERS_MAX
- AUTO_TURBO_BIT
- BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE
- BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES
- BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS
- BLOCK_RAM_TO_MLAB_CELL_CONVERSION
- C3_M9K_BIT_SKIP
- CARRY_OUT_PINS_LCELL_INSERT
- CDR_BANDWIDTH_PRESET
- CKN_CK_PAIR
- CLAMPING_DIODE
- CLOCK_ENABLE_ROUTING
- CLOCK_REGION
- CLOCK_TO_OUTPUT_DELAY
- CONFIGURATION_VCCIO_LEVEL
- CRC_ERROR_CHECKING
- CRC_ERROR_OPEN_DRAIN
- CURRENT_STRENGTH_NEW
- CVP_CONFDONE_OPEN_DRAIN
- CVP_MODE
- CYCLONEIII_CONFIGURATION_SCHEME
- CYCLONEII_CONFIGURATION_SCHEME
- CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION
- CYCLONEII_TERMINATION
- CYCLONE_CONFIGURATION_SCHEME
- D1_DELAY
- D1_FINE_DELAY
- D2_DELAY
- D3_DELAY
- D4_DELAY
- D4_FINE_DELAY
- D5_DELAY
- D5_FINE_DELAY
- D5_OCT_DELAY
- D5_OE_DELAY
- D6_DELAY
- D6_FINE_DELAY
- D6_OCT_DELAY
- D6_OE_DELAY
- D6_OE_FINE_DELAY
- DATA0_PIN
- DCLK_PIN
- DC_CURRENT_FOR_ELECTROMIGRATION_CHECK
- DDIO_INPUT_REGISTER
- DDIO_OUTPUT_REGISTER
- DDIO_OUTPUT_REGISTER_DISTANCE
- DECREASE_INPUT_DELAY_TO_INPUT_REGISTER
- DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER
- DELAY_SETTING_FROM_VIO_TO_CORE
- DEVICE
- DEVICE_INITIALIZATION_CLOCK
- DEVICE_MIGRATION_LIST
- DEVICE_TECHNOLOGY_MIGRATION_LIST
- DM_PIN
- DPRIO_CHANNEL_NUM
- DPRIO_CRUCLK_NUM
- DPRIO_INTERFACE_REG
- DPRIO_QUAD_NUM
- DPRIO_QUAD_PLL_NUM
- DPRIO_TX_PLL0_REFCLK_NUM
- DPRIO_TX_PLL1_REFCLK_NUM
- DPRIO_TX_PLL_NUM
- DQSB_DQS_PAIR
- DQSOUT_DELAY_CHAIN
- DQS_ENABLE_DELAY_CHAIN
- DQS_LOCAL_CLOCK_DELAY_CHAIN
- DQ_GROUP
- DQ_PIN
- DUAL_PURPOSE_CLOCK_PIN_DELAY
- DUPLICATE_ATOM
- DYNAMIC_OCT_CONTROL_GROUP
- ECO_ALLOW_ROUTING_CHANGES
- ECO_OPTIMIZE_TIMING
- ECO_REGENERATE_REPORT
- ENABLE_ASMI_FOR_FLASH_LOADER
- ENABLE_BENEFICIAL_SKEW_OPTIMIZATION
- ENABLE_BOOT_SEL_PIN
- ENABLE_BUS_HOLD_CIRCUITRY
- ENABLE_CONFIGURATION_PINS
- ENABLE_CRC_ERROR_PIN
- ENABLE_CVP_CONFDONE
- ENABLE_DEVICE_WIDE_OE
- ENABLE_DEVICE_WIDE_RESET
- ENABLE_HOLD_BACK_OFF
- ENABLE_INIT_DONE_OUTPUT
- ENABLE_JTAG_BST_SUPPORT
- ENABLE_JTAG_PIN_SHARING
- ENABLE_NCEO_OUTPUT
- ENABLE_NCE_PIN
- ENABLE_NCONFIG_FROM_CORE
- ENABLE_PR_PINS
- ENABLE_VREFA_PIN
- ENABLE_VREFB_PIN
- ERROR_CHECK_FREQUENCY_DIVISOR
- EXCLUSIVE_IO_GROUP
- EXTERNAL_FLASH_FALLBACK_ADDRESS
- EXTERNAL_LVDS_RX_USES_DPA
- FALLBACK_TO_EXTERNAL_FLASH
- FASTROW_INTERCONNECT
- FINAL_PLACEMENT_OPTIMIZATION
- FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND
- FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION
- FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN
- FITTER_EARLY_TIMING_ESTIMATE_MODE
- FITTER_EFFORT
- FIT_ATTEMPTS_TO_SKIP
- FIT_ONLY_ONE_ATTEMPT
- FLEX10K_CONFIGURATION_SCHEME
- FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
- FLEX10K_DEVICE_IO_STANDARD
- FLEX10K_ENABLE_LOCK_OUTPUT
- FLEX10K_MAX_PERIPHERAL_OE
- FLEX6K_CONFIGURATION_SCHEME
- FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
- FLEX6K_DEVICE_IO_STANDARD
- FORCE_CONFIGURATION_VCCIO
- FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS
- FORCE_FRACTURED_MODE_ALM_IMPLEMENTATION
- FORCE_MERGE_PLL
- FORCE_MERGE_PLL_FANOUTS
- FORCE_NON_FRACTURED_MODE_ALM_IMPLEMENTATION
- FORM_DDR_CLUSTERING_CLIQUE
- GENERATE_GXB_RECONFIG_MIF
- GENERATE_GXB_RECONFIG_MIF_WITH_PLL
- GLOBAL_SIGNAL
- GLOBAL_SIGNAL_CLKCTRL_LOCATION
- GNDIO_CURRENT_1PT8V
- GNDIO_CURRENT_2PT5V
- GNDIO_CURRENT_GTL
- GNDIO_CURRENT_GTL_PLUS
- GNDIO_CURRENT_LVCMOS
- GNDIO_CURRENT_LVTTL
- GNDIO_CURRENT_PCI
- GNDIO_CURRENT_SSTL2_CLASS1
- GNDIO_CURRENT_SSTL2_CLASS2
- GNDIO_CURRENT_SSTL3_CLASS1
- GNDIO_CURRENT_SSTL3_CLASS2
- GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME
- GXB_0PPM_CLOCK_GROUP
- GXB_0PPM_CLOCK_GROUP_DRIVER
- GXB_0PPM_CORECLK
- GXB_0PPM_CORE_CLOCK
- GXB_CLOCK_GROUP
- GXB_CLOCK_GROUP_DRIVER
- GXB_RECONFIG_GROUP
- GXB_RECONFIG_MIF
- GXB_RECONFIG_MIF_PLL
- GXB_REFCLK_COUPLING_TERMINATION_SETTING
- GXB_RESERVED_TRANSMIT_CHANNEL
- GXB_TX_PLL_RECONFIG_GROUP
- HPS_IO
- IGNORE_MODE_FOR_MERGE
- IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE
- INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN
- INCREASE_DELAY_TO_OUTPUT_PIN
- INCREASE_INPUT_CLOCK_ENABLE_DELAY
- INCREASE_INPUT_DELAY_TO_CE_IO_REGISTER
- INCREASE_OUTPUT_CLOCK_ENABLE_DELAY
- INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY
- INCREASE_TZX_DELAY_TO_OUTPUT_PIN
- INC_PLC_MODE
- INIT_DONE_OPEN_DRAIN
- INPUT_DELAY_CHAIN
- INPUT_REFERENCE
- INPUT_TERMINATION
- INSERT_ADDITIONAL_LOGIC_CELL
- INTERNAL_FLASH_UPDATE_MODE
- INTERNAL_SCRUBBING
- IO_12_LANE_INPUT_DATA_DELAY_CHAIN
- IO_12_LANE_INPUT_STROBE_DELAY_CHAIN
- IO_MAXIMUM_TOGGLE_RATE
- IO_PLACEMENT_OPTIMIZATION
- IO_STANDARD
- LVDS_DIRECT_LOOPBACK_MODE
- LVDS_RX_REGISTER
- M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY
- MATCH_PLL_COMPENSATION_CLOCK
- MAX10FPGA_CONFIGURATION_SCHEME
- MAX7000B_VCCIO_IOBANK1
- MAX7000B_VCCIO_IOBANK2
- MAX7000_DEVICE_IO_STANDARD
- MAX7000_ENABLE_JTAG_BST_SUPPORT
- MAX7000_INDIVIDUAL_TURBO_BIT
- MAX_CLOCKS_ALLOWED
- MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATION
- MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATION
- MAX_CURRENT_FOR_ELECTROMIGRATION
- MAX_CURRENT_FOR_VIO_ELECTROMIGRATION
- MAX_GLOBAL_CLOCKS_ALLOWED
- MAX_PERIPHERY_CLOCKS_ALLOWED
- MAX_REGIONAL_CLOCKS_ALLOWED
- MEMORY_INTERFACE_DATA_PIN_GROUP
- MEM_INTERFACE_DELAY_CHAIN_CONFIG
- MERCURY_CONFIGURATION_SCHEME
- MERCURY_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
- MERCURY_DEVICE_IO_STANDARD
- MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEAR
- MIGRATION_CONSTRAIN_CORE_RESOURCES
- MIGRATION_DEVICES
- NCEO_OPEN_DRAIN
- NDQS_LOCAL_CLOCK_DELAY_CHAIN
- NORMAL_LCELL_INSERT
- OE_DELAY_CHAIN
- OPTIMIZE_FOR_METASTABILITY
- OPTIMIZE_HOLD_TIMING
- OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING
- OPTIMIZE_MULTI_CORNER_TIMING
- OPTIMIZE_POWER_DURING_FITTING
- OPTIMIZE_SSN
- OPTIMIZE_TIMING
- OUTPUT_BUFFER_DELAY
- OUTPUT_BUFFER_DELAY_CONTROL
- OUTPUT_DELAY_CHAIN
- OUTPUT_ENABLE_DELAY
- OUTPUT_ENABLE_GROUP
- OUTPUT_ENABLE_REGISTER_DUPLICATION
- OUTPUT_ENABLE_ROUTING
- OUTPUT_PIN_LOAD
- OUTPUT_TERMINATION
- OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS
- PAD_TO_CORE_DELAY
- PAD_TO_DDIO_REGISTER_DELAY
- PAD_TO_INPUT_REGISTER_DELAY
- PCI_IO
- PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING
- PHYSICAL_SYNTHESIS_COMBO_LOGIC
- PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA
- PHYSICAL_SYNTHESIS_EFFORT
- PHYSICAL_SYNTHESIS_LOG_FILE
- PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA
- PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION
- PHYSICAL_SYNTHESIS_REGISTER_RETIMING
- PLACEMENT_EFFORT_MULTIPLIER
- PLL_AUTO_RESET
- PLL_BANDWIDTH_PRESET
- PLL_CHANNEL_SPACING
- PLL_COMPENSATE
- PLL_COMPENSATION_MODE
- PLL_ENFORCE_USER_PHASE_SHIFT
- PLL_FEEDBACK_CLOCK_SIGNAL
- PLL_FORCE_OUTPUT_COUNTER
- PLL_FORCE_OUTPUT_COUNTER_HARDCOPY_REPLAY
- PLL_IGNORE_MIGRATION_DEVICES
- PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING
- PLL_OUTPUT_CLOCK_FREQUENCY
- PLL_PFD_CLOCK_FREQUENCY
- PLL_TYPE
- PLL_VCO_CLOCK_FREQUENCY
- PRESERVE_PLL_COUNTER_ORDER
- PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES
- PROGRAMMABLE_POWER_TECHNOLOGY_SETTING
- PROGRAMMABLE_PREEMPHASIS
- PROGRAMMABLE_VOD
- PR_DONE_OPEN_DRAIN
- PR_ERROR_OPEN_DRAIN
- PR_PINS_OPEN_DRAIN
- PR_READY_OPEN_DRAIN
- QDR_D_PIN_GROUP
- QII_AUTO_PACKED_REGISTERS
- RESERVE_ALL_UNUSED_PINS
- RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP
- RESERVE_ASDO_AFTER_CONFIGURATION
- RESERVE_DATA0_AFTER_CONFIGURATION
- RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION
- RESERVE_DATA1_AFTER_CONFIGURATION
- RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION
- RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION
- RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION
- RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION
- RESERVE_DCLK_AFTER_CONFIGURATION
- RESERVE_FLASH_NCE_AFTER_CONFIGURATION
- RESERVE_FLEXIBLE_CLOCK_NETWORK
- RESERVE_NCEO_AFTER_CONFIGURATION
- RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION
- RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION
- RESERVE_RDYNBUSY_AFTER_CONFIGURATION
- ROUTER_CLOCKING_TOPOLOGY_ANALYSIS
- ROUTER_EFFORT_MULTIPLIER
- ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION
- ROUTER_REGISTER_DUPLICATION
- ROUTER_TIMING_OPTIMIZATION_LEVEL
- ROW_GLOBAL_SIGNAL
- RZQ_GROUP
- SCE_PIN
- SDO_PIN
- SEED
- SLEW_RATE
- SLOW_SLEW_RATE
- STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET
- STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE
- STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE
- STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B
- STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER
- STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE
- STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE
- STRATIXGX_ALLOW_POST8B10B_LOOPBACK
- STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK
- STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE
- STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS
- STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE
- STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER
- STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE
- STRATIXGX_TERMINATION_VALUE
- STRATIXIIGX_TERMINATION_VALUE
- STRATIXIII_CONFIGURATION_SCHEME
- STRATIXIII_MRAM_COMPATIBILITY
- STRATIXIII_UPDATE_MODE
- STRATIXII_CONFIGURATION_SCHEME
- STRATIXII_TERMINATION
- STRATIXV_CONFIGURATION_SCHEME
- STRATIX_CONFIGURATION_SCHEME
- STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
- STRATIX_DEVICE_IO_STANDARD
- STRATIX_UPDATE_MODE
- SYNCHRONIZER_IDENTIFICATION
- SYNCHRONIZER_TOGGLE_RATE
- T11_0_DELAY
- T11_1_DELAY
- T11_DELAY
- T11_FINE_DELAY
- T4_DELAY
- T8_DELAY0
- T8_DELAY1
- TERMINATION
- TERMINATION_CONTROL_BLOCK
- TREAT_BIDIR_AS_OUTPUT
- TRI_STATE_SPI_PINS
- TURBO_BIT
- TXPMA_SLEW_RATE
- UNFORCE_MERGE_PLL
- UNFORCE_MERGE_PLL_OUTPUT_COUNTER
- UNUSED_TSD_PINS_GND
- USER_START_UP_CLOCK
- VCCIO_CURRENT_1PT8V
- VCCIO_CURRENT_2PT5V
- VCCIO_CURRENT_GTL
- VCCIO_CURRENT_GTL_PLUS
- VCCIO_CURRENT_LVCMOS
- VCCIO_CURRENT_LVTTL
- VCCIO_CURRENT_PCI
- VCCIO_CURRENT_SSTL2_CLASS1
- VCCIO_CURRENT_SSTL2_CLASS2
- VCCIO_CURRENT_SSTL3_CLASS1
- VCCIO_CURRENT_SSTL3_CLASS2
- VCCPD_VOLTAGE
- VREF_MODE
- WEAK_PULL_UP_RESISTOR
- XCVR_A10_REFCLK_TERM_TRISTATE
- XCVR_A10_RX_ADP_CTLE_ACGAIN_4S
- XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL
- XCVR_A10_RX_ADP_DFE_FXTAP1
- XCVR_A10_RX_ADP_DFE_FXTAP2
- XCVR_A10_RX_ADP_DFE_FXTAP3
- XCVR_A10_RX_ADP_DFE_FXTAP4
- XCVR_A10_RX_ADP_DFE_FXTAP5
- XCVR_A10_RX_ADP_DFE_FXTAP6
- XCVR_A10_RX_ADP_DFE_FXTAP7
- XCVR_A10_RX_ADP_VGA_SEL
- XCVR_A10_RX_EQ_DC_GAIN_TRIM
- XCVR_A10_RX_LINK
- XCVR_A10_RX_ONE_STAGE_ENABLE
- XCVR_A10_RX_TERM_SEL
- XCVR_A10_TX_COMPENSATION_EN
- XCVR_A10_TX_LINK
- XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP
- XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP
- XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T
- XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T
- XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
- XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
- XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
- XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
- XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL
- XCVR_ANALOG_SETTINGS_PROTOCOL
- XCVR_GT_IO_PIN_TERMINATION
- XCVR_GT_RX_COMMON_MODE_VOLTAGE
- XCVR_GT_RX_CTLE
- XCVR_GT_RX_DC_GAIN
- XCVR_GT_TX_COMMON_MODE_VOLTAGE
- XCVR_GT_TX_PRE_EMP_1ST_POST_TAP
- XCVR_GT_TX_PRE_EMP_INV_PRE_TAP
- XCVR_GT_TX_PRE_EMP_PRE_TAP
- XCVR_GT_TX_VOD_MAIN_TAP
- XCVR_IO_PIN_TERMINATION
- XCVR_RECONFIG_GROUP
- XCVR_REFCLK_PIN_TERMINATION
- XCVR_RX_ACGAIN_A
- XCVR_RX_ACGAIN_V
- XCVR_RX_BYPASS_EQ_STAGES_234
- XCVR_RX_COMMON_MODE_VOLTAGE
- XCVR_RX_DC_GAIN
- XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE
- XCVR_RX_EQ_BW_SEL
- XCVR_RX_INPUT_VCM_SEL
- XCVR_RX_LINEAR_EQUALIZER_CONTROL
- XCVR_RX_SD_ENABLE
- XCVR_RX_SD_OFF
- XCVR_RX_SD_ON
- XCVR_RX_SD_THRESHOLD
- XCVR_RX_SEL_HALF_BW
- XCVR_TX_COMMON_MODE_VOLTAGE
- XCVR_TX_PLL_RECONFIG_GROUP
- XCVR_TX_PRE_EMP_1ST_POST_TAP
- XCVR_TX_PRE_EMP_2ND_POST_TAP
- XCVR_TX_PRE_EMP_2ND_POST_TAP_USER
- XCVR_TX_PRE_EMP_INV_2ND_TAP
- XCVR_TX_PRE_EMP_INV_PRE_TAP
- XCVR_TX_PRE_EMP_PRE_TAP
- XCVR_TX_PRE_EMP_PRE_TAP_USER
- XCVR_TX_RX_DET_ENABLE
- XCVR_TX_RX_DET_MODE
- XCVR_TX_RX_DET_OUTPUT_SEL
- XCVR_TX_SLEW_RATE_CTRL
- XCVR_TX_VCM_CTRL_SRC
- XCVR_TX_VOD
- XCVR_TX_VOD_PRE_EMP_CTRL_SRC
- XCVR_VCCA_VOLTAGE
- XCVR_VCCR_VCCT_VOLTAGE
- XSTL_INPUT_ALLOW_SE_BUFFER
- Incremental Compilation Assignments
- ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS
- ALLOW_MULTIPLE_PERSONAS
- AUTO_EXPORT_INCREMENTAL_COMPILATION
- CROSS_BOUNDARY_OPTIMIZATIONS
- ENABLE_LAB_SHARING_WITH_PARENT_PARTITION
- ENABLE_STRICT_PRESERVATION
- EXTENDS_TOP_BLOCK
- IGNORE_PARTITIONS
- IMPORT_BLOCK
- INCREMENTAL_COMPILATION_EXPORT_FILE
- INCREMENTAL_COMPILATION_EXPORT_FLATTEN
- INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAME
- INCREMENTAL_COMPILATION_EXPORT_POST_FIT
- INCREMENTAL_COMPILATION_EXPORT_POST_SYNTH
- INCREMENTAL_COMPILATION_EXPORT_ROUTING
- INPUT_PERSONA
- INSERT_BOUNDARY_WIRE_LUTS
- MERGE_EQUIVALENT_BIDIRS
- MERGE_EQUIVALENT_INPUTS
- PARTIAL_RECONFIGURATION_PARTITION
- PARTITION_ALWAYS_USE_QXP_NETLIST
- PARTITION_ASD_REGION_ID
- PARTITION_ENABLE_STRICT_PRESERVATION
- PARTITION_FITTER_PRESERVATION_LEVEL
- PARTITION_HIERARCHY
- PARTITION_IGNORE_SOURCE_FILE_CHANGES
- PARTITION_IMPORT_ASSIGNMENTS
- PARTITION_IMPORT_EXISTING_ASSIGNMENTS
- PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS
- PARTITION_IMPORT_FILE
- PARTITION_IMPORT_PROMOTE_ASSIGNMENTS
- PARTITION_LAST_IMPORTED_FILE
- PARTITION_NETLIST_TYPE
- PARTITION_PRESERVE_HIGH_SPEED_TILES
- PROPAGATE_CONSTANTS_ON_INPUTS
- PROPAGATE_INVERSIONS_ON_INPUTS
- QDB_FILE
- QDB_PATH
- QHD_MODE
- RAPID_RECOMPILE_ASSIGNMENT_CHECKING
- REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS
- LogicLock Region Assignments
- Migration Assignments
- Netlist Viewer Assignments
- Pin & Location Assignments
- APEX20K_CLIQUE_TYPE
- APEX20K_LOCAL_ROUTING_SOURCE
- FAST_INPUT_REGISTER
- FAST_OCT_REGISTER
- FAST_OUTPUT_ENABLE_REGISTER
- FAST_OUTPUT_REGISTER
- FLEX10K_CLIQUE_TYPE
- FLEX6K_CLIQUE_TYPE
- FLEX6K_LOCAL_ROUTING_SOURCE
- IP_DEBUG_VISIBLE
- LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT
- LOCATION
- MAX7K_CLIQUE_TYPE
- MEMBER_OF
- MERCURY_CLIQUE_TYPE
- PIN_CONNECT_FROM_NODE
- RESERVE_PIN
- SUBCLIQUE_OF
- VIRTUAL_PIN
- Power Estimation Assignments
- ENABLE_SMART_VOLTAGE_ID
- POWER_AUTO_COMPUTE_TJ
- POWER_BOARD_TEMPERATURE
- POWER_BOARD_THERMAL_MODEL
- POWER_DEFAULT_INPUT_IO_TOGGLE_RATE
- POWER_DEFAULT_TOGGLE_RATE
- POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR
- POWER_HPS_DYNAMIC_POWER_DUAL
- POWER_HPS_DYNAMIC_POWER_SINGLE
- POWER_HPS_ENABLE
- POWER_HPS_JUNCTION_TEMPERATURE
- POWER_HPS_PROC_FREQ
- POWER_HPS_STATIC_POWER
- POWER_HPS_TOTAL_POWER
- POWER_HSSI
- POWER_HSSI_LEFT
- POWER_HSSI_RIGHT
- POWER_HSSI_VCCHIP_LEFT
- POWER_HSSI_VCCHIP_RIGHT
- POWER_INPUT_FILE_NAME
- POWER_INPUT_FILE_TYPE
- POWER_INPUT_SAF_NAME
- POWER_INPUT_VCD_FILE_NAME
- POWER_OCS_VALUE
- POWER_OJB_VALUE
- POWER_OJC_VALUE
- POWER_OSA_VALUE
- POWER_OUTPUT_SAF_NAME
- POWER_PRESET_COOLING_SOLUTION
- POWER_READ_INPUT_FILE
- POWER_REPORT_POWER_DISSIPATION
- POWER_REPORT_SIGNAL_ACTIVITY
- POWER_SIGNAL_ACTIVITY_END_TIME
- POWER_SIGNAL_ACTIVITY_START_TIME
- POWER_STATIC_PROBABILITY
- POWER_TJ_VALUE
- POWER_TOGGLE_RATE
- POWER_TOGGLE_RATE_PERCENTAGE
- POWER_USE_CUSTOM_COOLING_SOLUTION
- POWER_USE_DEVICE_CHARACTERISTICS
- POWER_USE_INPUT_FILE
- POWER_USE_INPUT_FILES
- POWER_USE_PVA
- POWER_USE_TA_VALUE
- POWER_VCCAUX_USER_OPTION
- POWER_VCCA_GXBL_USER_OPTION
- POWER_VCCA_GXBR_USER_OPTION
- POWER_VCCA_GXB_USER_OPTION
- POWER_VCCA_L_USER_OPTION
- POWER_VCCA_R_USER_OPTION
- POWER_VCCCB_USER_OPTION
- POWER_VCCH_GXBL_USER_OPTION
- POWER_VCCH_GXBR_USER_OPTION
- POWER_VCCH_GXB_USER_OPTION
- POWER_VCCIO_USER_OPTION
- POWER_VCCL_GXB_USER_OPTION
- POWER_VCCPD_USER_OPTION
- POWER_VCCR_GXBL_USER_OPTION
- POWER_VCCR_GXBR_USER_OPTION
- POWER_VCCR_GXB_USER_OPTION
- POWER_VCCT_GXBL_USER_OPTION
- POWER_VCCT_GXBR_USER_OPTION
- POWER_VCCT_GXB_USER_OPTION
- POWER_VCD_FILE_END_TIME
- POWER_VCD_FILE_START_TIME
- POWER_VCD_FILTER_GLITCHES
- VCCAUX_SHARED_USER_VOLTAGE
- VCCAUX_USER_VOLTAGE
- VCCA_FPLL_USER_VOLTAGE
- VCCA_GTBR_USER_VOLTAGE
- VCCA_GTB_USER_VOLTAGE
- VCCA_GXBL_USER_VOLTAGE
- VCCA_GXBR_USER_VOLTAGE
- VCCA_GXB_USER_VOLTAGE
- VCCA_L_USER_VOLTAGE
- VCCA_PLL_USER_VOLTAGE
- VCCA_R_USER_VOLTAGE
- VCCA_USER_VOLTAGE
- VCCBAT_USER_VOLTAGE
- VCCCB_USER_VOLTAGE
- VCCD_FPLL_USER_VOLTAGE
- VCCD_PLL_USER_VOLTAGE
- VCCD_USER_VOLTAGE
- VCCEH_GXBL_USER_VOLTAGE
- VCCEH_GXBR_USER_VOLTAGE
- VCCEH_GXB_USER_VOLTAGE
- VCCE_GXBL_USER_VOLTAGE
- VCCE_GXBR_USER_VOLTAGE
- VCCE_GXB_USER_VOLTAGE
- VCCE_USER_VOLTAGE
- VCCHIP_L_USER_VOLTAGE
- VCCHIP_R_USER_VOLTAGE
- VCCHIP_USER_VOLTAGE
- VCCHSSI_L_USER_VOLTAGE
- VCCHSSI_R_USER_VOLTAGE
- VCCH_GTBR_USER_VOLTAGE
- VCCH_GTB_USER_VOLTAGE
- VCCH_GXBL_USER_VOLTAGE
- VCCH_GXBR_USER_VOLTAGE
- VCCH_GXB_USER_VOLTAGE
- VCCH_L_USER_VOLTAGE
- VCCH_R_USER_VOLTAGE
- VCCINT_USER_VOLTAGE
- VCCIO_USER_VOLTAGE
- VCCL_GTBL_USER_VOLTAGE
- VCCL_GTBR_USER_VOLTAGE
- VCCL_GTB_USER_VOLTAGE
- VCCL_GXBL_USER_VOLTAGE
- VCCL_GXBR_USER_VOLTAGE
- VCCL_GXB_USER_VOLTAGE
- VCCL_USER_VOLTAGE
- VCCPD_USER_VOLTAGE
- VCCPGM_USER_VOLTAGE
- VCCPLL_HPS_USER_VOLTAGE
- VCCPT_USER_VOLTAGE
- VCCP_USER_VOLTAGE
- VCCRSTCLK_HPS_USER_VOLTAGE
- VCCR_GTBL_USER_VOLTAGE
- VCCR_GTBR_USER_VOLTAGE
- VCCR_GTB_USER_VOLTAGE
- VCCR_GXBL_USER_VOLTAGE
- VCCR_GXBR_USER_VOLTAGE
- VCCR_GXB_USER_VOLTAGE
- VCCR_L_USER_VOLTAGE
- VCCR_R_USER_VOLTAGE
- VCCR_USER_VOLTAGE
- VCCT_GTBL_USER_VOLTAGE
- VCCT_GTBR_USER_VOLTAGE
- VCCT_GTB_USER_VOLTAGE
- VCCT_GXBL_USER_VOLTAGE
- VCCT_GXBR_USER_VOLTAGE
- VCCT_GXB_USER_VOLTAGE
- VCCT_L_USER_VOLTAGE
- VCCT_R_USER_VOLTAGE
- VCCT_USER_VOLTAGE
- VCC_HPS_USER_VOLTAGE
- VCC_USER_VOLTAGE
- Programmer Assignments
- GENERATE_CONFIG_HEXOUT_FILE
- GENERATE_CONFIG_ISC_FILE
- GENERATE_CONFIG_JAM_FILE
- GENERATE_CONFIG_JBC_FILE
- GENERATE_CONFIG_JBC_FILE_COMPRESSED
- GENERATE_CONFIG_SVF_FILE
- GENERATE_ISC_FILE
- GENERATE_JAM_FILE
- GENERATE_JBC_FILE
- GENERATE_JBC_FILE_COMPRESSED
- GENERATE_SVF_FILE
- HPS_EARLY_IO_RELEASE
- ISP_CLAMP_STATE
- ISP_CLAMP_STATE_DEFAULT
- MERGE_HEX_FILE
- Project-Wide Assignments
- AGGREGATE_REVISION
- AHDL_FILE
- AHDL_TEXT_DESIGN_OUTPUT_FILE
- ASM_FILE
- AUTO_EXPORT_VER_COMPATIBLE_DB
- BASE_REVISION
- BASE_REVISION_PROJECT_OUTPUT_DIRECTORY
- BDF_FILE
- BINARY_FILE
- BSF_FILE
- CDF_FILE
- COMMAND_MACRO_FILE
- CPP_FILE
- CPP_INCLUDE_FILE
- CUSP_FILE
- CVP_REVISION
- C_FILE
- DEPENDENCY_FILE
- DSPBUILDER_FILE
- EDIF_FILE
- ELF_FILE
- ENABLE_COMPACT_REPORT_TABLE
- ENABLE_REDUCED_MEMORY_MODE
- EQUATION_FILE
- FLOW_DISABLE_ASSEMBLER
- FLOW_ENABLE_HC_COMPARE
- FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS
- FLOW_ENABLE_PARALLEL_MODULES
- FLOW_ENABLE_POWER_ANALYZER
- FLOW_ENABLE_RTL_VIEWER
- FLOW_HARDCOPY_DESIGN_READINESS_CHECK
- GDF_FILE
- HC_OUTPUT_DIR
- HEX_FILE
- HEX_OUTPUT_FILE
- HPS_ISW_FILE
- HTML_FILE
- HTML_REPORT_FILE
- INCLUDE_FILE
- IPA_FILE
- IPX_FILE
- IP_COMPONENT_AUTHOR
- IP_COMPONENT_DESCRIPTION
- IP_COMPONENT_DISPLAY_NAME
- IP_COMPONENT_DOCUMENTATION_LINK
- IP_COMPONENT_GROUP
- IP_COMPONENT_INTERNAL
- IP_COMPONENT_NAME
- IP_COMPONENT_PARAMETER
- IP_COMPONENT_REPORT_HIERARCHY
- IP_COMPONENT_VERSION
- IP_GENERATED_DEVICE_FAMILY
- IP_QSYS_MODE
- IP_TARGETED_DEVICE_FAMILY
- IP_TARGETED_PART_TRAIT
- IP_TOOL_ENV
- IP_TOOL_HIERARCHY_LEVELS
- IP_TOOL_NAME
- IP_TOOL_VERSION
- ISC_FILE
- JAM_FILE
- JBC_FILE
- LICENSE_FILE
- LMF_FILE
- LOGIC_ANALYZER_INTERFACE_FILE
- MAP_FILE
- MASK_REVISION
- MESSAGE_DISABLE
- MESSAGE_ENABLE
- MIF_FILE
- MIGRATION_DIFFERENT_SOURCE_FILE
- MISC_FILE
- NUM_PARALLEL_PROCESSORS
- OBJECT_FILE
- OCP_FILE
- PARTIAL_SRAM_OBJECT_FILE
- PDC_FILE
- PERSONA_FILE
- PIN_FILE
- POWER_INPUT_FILE
- PPF_FILE
- PROGRAMMER_OBJECT_FILE
- PROJECT_OUTPUT_DIRECTORY
- PROJECT_SHOW_ENTITY_NAME
- PROJECT_USE_SIMPLIFIED_NAMES
- QARLOG_FILE
- QAR_FILE
- QIP_FILE
- QSYS_FILE
- QUARTUS_PTF_FILE
- QUARTUS_SBD_FILE
- QUARTUS_STANDARD_DELAY_FILE
- QVAR_FILE
- QXP_FILE
- RAW_BINARY_FILE
- READ_OR_WRITE_IN_BYTE_ADDRESS
- RECONFIGURABLE_REVISION
- REVISION_TYPE
- RUN_FULL_COMPILE_ON_DEVICE_CHANGE
- SAVE_MIGRATION_INFO_DURING_COMPILATION
- SBI_FILE
- SDC_FILE
- SDF_OUTPUT_FILE
- SERIAL_BITSTREAM_FILE
- SIGNALTAP_FILE
- SIP_FILE
- SLD_FILE
- SMF_FILE
- SOFTWARE_LIBRARY_FILE
- SOPCINFO_FILE
- SOPC_FILE
- SOURCE_TCL_SCRIPT_FILE
- SPD_FILE
- SRAM_OBJECT_FILE
- SRECORDS_FILE
- SVF_FILE
- SYM_FILE
- SYNTHESIS_ONLY_QIP
- SYSTEMVERILOG_FILE
- TCL_SCRIPT_FILE
- TEMPLATE_FILE
- TEXT_FILE
- TEXT_FORMAT_REPORT_FILE
- TIMING_ANALYSIS_OUTPUT_FILE
- VCD_FILE
- VECTOR_TABLE_OUTPUT_FILE
- VECTOR_TEXT_FILE
- VECTOR_WAVEFORM_FILE
- VERILOG_FILE
- VERILOG_INCLUDE_FILE
- VERILOG_OUTPUT_FILE
- VERILOG_TEST_BENCH_FILE
- VER_COMPATIBLE_DB_DIR
- VHDL_FILE
- VHDL_OUTPUT_FILE
- VHDL_TEST_BENCH_FILE
- VQM_FILE
- ZIP_VECTOR_WAVEFORM_FILE
- SignalProbe Assignments
- SignalTap II Assignments
- Simulator Assignments
- ACTION
- ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS
- ADD_TO_SIMULATION_OUTPUT_WAVEFORMS
- ALIAS
- AUTO_USE_SIMULATION_PDB_NETLIST
- BREAKPOINT_STATE
- CHECK_OUTPUTS
- END_TIME
- EXTERNAL_PIN_CONNECTION
- GLITCH_DETECTION
- GLITCH_INTERVAL
- IMMEDIATE_ASSERTION_FAIL_ACTION
- IMMEDIATE_ASSERTION_FAIL_MESSAGE
- IMMEDIATE_ASSERTION_PASS_MESSAGE
- IMMEDIATE_ASSERTION_STATE
- IMMEDIATE_ASSERTION_TEST_CONDITION
- INCREMENTAL_VECTOR_INPUT_SOURCE
- PASSIVE_RESISTOR
- SETUP_HOLD_DETECTION
- SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED
- SETUP_HOLD_TIME_VIOLATION_DETECTION
- SIMULATION_BUS_CHANNEL_GROUPING
- SIMULATION_CELL_DELAY_MODEL_TYPE
- SIMULATION_COMPARE_SIGNAL
- SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL
- SIMULATION_COVERAGE
- SIMULATION_DEFAULT_VECTOR_COMPARE_TOLERANCE
- SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE
- SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL
- SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL
- SIMULATION_MODE
- SIMULATION_NETLIST_VIEWER
- SIMULATION_SIGNAL_COMPARE_TOLERANCE
- SIMULATION_VDB_RESULT_FLUSH
- SIMULATION_VECTOR_COMPARE_BEGIN_TIME
- SIMULATION_VECTOR_COMPARE_END_TIME
- SIMULATION_VECTOR_COMPARE_RULE_FOR_0
- SIMULATION_VECTOR_COMPARE_RULE_FOR_1
- SIMULATION_VECTOR_COMPARE_RULE_FOR_DC
- SIMULATION_VECTOR_COMPARE_RULE_FOR_H
- SIMULATION_VECTOR_COMPARE_RULE_FOR_L
- SIMULATION_VECTOR_COMPARE_RULE_FOR_U
- SIMULATION_VECTOR_COMPARE_RULE_FOR_W
- SIMULATION_VECTOR_COMPARE_RULE_FOR_X
- SIMULATION_VECTOR_COMPARE_RULE_FOR_Z
- SIMULATION_WITH_AUTO_GLITCH_FILTERING
- SIMULATION_WITH_GLITCH_FILTERING_IN_NORMAL_FLOW
- SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF
- SIMULATOR_GENERATE_POWERPLAY_VCD_FILE
- SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE
- SIMULATOR_POWERPLAY_VCD_FILE_END_TIME
- SIMULATOR_POWERPLAY_VCD_FILE_OUTPUT_DESTINATION
- SIMULATOR_POWERPLAY_VCD_FILE_START_TIME
- SIMULATOR_PVT_TIMING_MODEL_TYPE
- SIMULATOR_SIGNAL_ACTIVITY_FILE_END_TIME
- SIMULATOR_SIGNAL_ACTIVITY_FILE_OUTPUT_DESTINATION
- SIMULATOR_SIGNAL_ACTIVITY_FILE_START_TIME
- SIM_BEHAVIOR_SIMULATION
- SIM_COMPILE_HDL_FILES
- SIM_HDL_TOP_MODULE_NAME
- SIM_OVERWRITE_WAVEFORM_INPUTS
- SIM_TAP_REGISTER_D_Q_PORTS
- SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE
- SIM_VECTOR_COMPARED_CLOCK_OFFSET
- SIM_VECTOR_COMPARED_CLOCK_PERIOD
- START_TIME
- TRIGGER_EQUATION
- TRIGGER_VECTOR_COMPARE_ON_SIGNAL
- USER_MESSAGE
- VECTOR_COMPARE_TRIGGER_MODE
- VECTOR_INPUT_SOURCE
- VECTOR_OUTPUT_DESTINATION
- VECTOR_OUTPUT_FORMAT
- X_ON_VIOLATION_OPTION
- Advanced I/O Timing Assignments