Document Outline

• RapidIO II MegaCore Function v14.0 and v14.0 Arria 10 Edition User Guide
  • Contents
  • 1. About The RapidIO II MegaCore Function
    • Features
      • New Features in the RapidIO II IP Core v14.0 and v14.0 Arria 10 Edition Releases
      • RapidIO II IP Core Features
      • Supported Transactions
    • Device Family Support
    • IP Core Verification
      • Simulation Testing
      • Hardware Testing
      • Interoperability Testing
    • Performance and Resource Utilization
    • Device Speed Grades
    • Release Information
    • Installation and Licensing
      • OpenCore Plus Evaluation
      • OpenCore Plus Time-Out Behavior
  • 2. Getting Started
    • Customizing and Generating IP Cores
    • IFiles Generated for Altera IP Cores (Legacy Parameter Editor)
    • IFiles Generated for Altera IP Cores by Qsys (Legacy Parameter Editor)
    • Files Generated for Altera IP Cores
    • Simulating IP Cores
      • Simulating the Testbench with the ModelSim Simulator
      • Simulating the Testbench with the VCS Simulator
    • Integrating Your IP Core in Your Design
      • Dynamic Transceiver Reconfiguration Controller for Arria V, Arria V GZ, Cyclone V, and Stratix V Variations
      • Transceiver PHY Reset Controller
      • Transceiver Settings
      • Adding Transceiver Analog Settings for Arria V GZ and Stratix V Variations
      • External Transceiver PLL
    • Compiling the Full Design and Programming the FPGA
    • Instantiating Multiple RapidIO II IP Cores
  • 3. Parameter Settings
    • Physical Layer Settings
      • Supported Modes
      • Maximum Baud Rate
      • Reference Clock Frequency
      • Enable Transceiver Dynamic Reconfiguration
    • Transport Layer Settings
      • Enable 16-Bit Device ID Width
      • Enable Avalon-ST Pass-Through Interface
      • Disable Destination ID Checking
    • Logical Layer Settings
      • Maintenance Configuration Settings
      • Doorbell Configuration Settings
      • I/O Master Configuration
      • I/O Slave Configuration
    • Capability Registers Settings
      • Device Identity CAR
        • Device ID
        • Vendor ID
      • Device Information CAR
        • Revision ID
      • Assembly Identity CAR
        • Assembly ID
        • Assembly Vendor ID
      • Assembly Information CAR
        • Revision ID
      • Processing Element Features CAR
        • Bridge Support
        • Memory Access
        • Processor Present
        • Enable Flow Arbitration Support
        • Enable Standard Route Table Configuration Support
        • Enable Extended Route Table Configuration Support
        • Enable Flow Control Support
        • Enable Switch Support
      • Switch Port Information CAR
        • Number of Ports
        • Port Number
      • Switch Route Table Destination ID Limit CAR
        • Switch Route Table Destination ID Limit
      • Data Streaming Information CAR
        • Maximum PDU
        • Number of Segmentation Contexts
      • Source Operations CAR
      • Destination Operations CAR
    • Command and Status Registers Settings
      • Data Streaming Logical Layer Control CSR
        • Supported Traffic Management Types Reset Value
        • Traffic Management Mode Reset Value
        • Maximum Transmission Unit Reset Value
      • Port General Control CSR
        • Host Reset Value
        • Master Enable Reset Value
        • Discovered Reset Value
      • Port 0 Control CSR
        • Flow Control Participant Reset Value
        • Enumeration Boundary Reset Value
        • Flow Arbitration Participant Reset Value
      • Lane n Status 0 CSR
        • Transmitter Type Reset Value
        • Receiver Type Reset Value
      • Extended Features Pointer CSR
    • Error Management Registers Settings
  • 4. Functional Description
    • Interfaces
      • Avalon Memory Mapped (Avalon-MM) Master and Slave Interfaces
        • Avalon-MM Interface Byte Ordering
      • Avalon Streaming (Avalon-ST) Interface
      • RapidIO Interface
    • Clocking and Reset Structure
      • Avalon System Clock
      • Reference Clock
      • Recovered Data Clock
      • Clock Rate Relationships in the RapidIO II IP Core
      • Clock Domains in Your Qsys System
      • Reset for RapidIO II IP Cores
    • Logical Layer Interfaces
      • Register Access Interface
        • Non-Doorbell Register Access Operations
        • Register Access Interface Signals
      • Input/Output Logical Layer Modules
        • Input/Output Avalon-MM Master Module
        • RapidIO Packet Data wdptr and Data Size Encoding in Avalon-MM Transactions
        • Input/Output Avalon-MM Master Module Timing Diagrams
        • Input/Output Avalon-MM Slave Module
        • Initiating Read and Write Transactions
        • Avalon-MM Burstcount and Byteenable Encoding in RapidIO Packets
        • Input/Output Avalon-MM Slave Module Timing Diagrams
      • Maintenance Module
        • Maintenance Interface Transactions
        • Maintenance Interface Signals
        • Initiating MAINTENANCE Read and Write Transactions
        • Responding to MAINTENANCE Read and Write Requests
        • Handling Port-Write Transactions
        • Maintenance Interface Transaction Examples
        • Maintenance Packet Error Handling
      • Doorbell Module
        • Doorbell Module Block Diagram
        • Preserving Transaction Order
        • Doorbell Module Signals
        • Generating a Doorbell Message
        • Receiving a Doorbell Message
      • Avalon-ST Pass-Through Interface
        • Transaction ID Ranges
        • Pass-Through Interface Signals
        • Pass-Through Interface Usage Examples
    • Transport Layer
      • Receiver
      • Transmitter
    • Physical Layer
      • Features
      • Physical Layer Interfaces
      • Low-level Interface Receiver
        • Receiver Transceiver
        • CRC Checking and Removal
      • Low-Level Interface Transmitter
    • Error Detection and Management
      • Physical Layer Error Management
        • Protocol Violations
        • Fatal Errors
      • Logical Layer Error Management
        • Maintenance Avalon-MM Slave
        • Maintenance Avalon-MM Master
        • Port-Write Reception Module
        • Port-Write Transmission Module
        • Input/Output Avalon-MM Slave
        • Input/Output Avalon-MM Master
      • Avalon-ST Pass-Through Interface
  • 5. Signals
    • Global Signals
    • Physical Layer Signals
      • Status Packet and Error Monitoring Signals
      • Low Latency Signals
        • Multicast Event Signals
        • Link-Request Reset-Device Signals
      • Transceiver Signals
      • Register-Related Signals
    • Logical and Transport Layer Signals
      • Avalon-MM Interface Signals
      • Avalon-ST Pass-Through Interface Signals
      • Data Streaming Support Signals
      • Packet and Error Monitoring Signal for the Transport Layer
    • Error Management Extension Signals
      • Error Reporting Signals
  • 6. Software Interface
    • Memory Map
    • Physical Layer Registers
    • Transport and Logical Layer Registers
      • Capability Registers (CARs)
      • Command and Status Registers (CSRs)
      • Maintenance Interrupt Control Registers
      • Transmit Maintenance Registers
      • Transmit Port-Write Registers
      • Receive Port-Write Registers
      • Input/Output Master Address Mapping Registers
      • Input/Output Master Interrupts
      • Input/Output Slave Mapping Registers
      • Input/Output Slave Interrupts
      • Input/Output Slave Pending Transactions
      • Error Management Registers
      • Doorbell Message Registers
  • 7. Testbench
    • Testbench Overview
    • Testbench Sequence
      • Reset, Initialization, and Configuration
      • Maintenance Write and Read Transactions
      • SWRITE Transactions
      • NREAD Transactions
      • NWRITE_R Transactions
      • NWRITE Transactions
      • Doorbell Transactions
      • Port-Write Transactions
      • Transactions Across the Avalon-ST Pass-Through Interface
    • Testbench Completion
    • Transceiver Level Connections in the Testbench
  • A. Initialization Sequence
  • B. Differences Between RapidIO II MegaCore Function v12.1 and RapidIO MegaCore Function v12.1
  • Additional Information
    • Document Revision History
    • How to Contact Altera
    • Typographic Conventions